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StefanSchippers / xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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[RFC] live op analysis + annotation #166

Closed qpwo closed 7 months ago

qpwo commented 7 months ago

Would be nice if there was a feature to rerun op analysis and re-annotate after every change you make to the circuit. Could speed up iteration a decent amount.

StefanSchippers commented 7 months ago

This is dangerous. On a big circuit an OP analysis takes time, it is not uncommon for a user to be faster changing a circuit than the simulator to complete. This must be handled in some way, for example stalling the editor until the OP has completed or killing the running sim if a change is made while previous OP still running. All these cases are difficult to make robust due to race conditions.

You can add a launcher.sym and bind the following command to it:

tclcommand="xschem netlist; simulate; xschem annotate_op"

For the above to work you must configure simulation to be launched in foreground mode, otherwise simulate will not block waiting for simulation to finish. Go to simulation -> Configure simulators and tools and set the 'fg' (Foreground) flag for the selected simulator.

If you are running interactive ngspice sims remember to put a quit 0 instruction at the end of your commands to quit the simulator, otherwise ngspice will keep running waiting for user input.

Control-Clcking on the launcher will trigger the associated commands.

StefanSchippers commented 7 months ago

Another smarter way is to set a callback to the simulate command, so you don't need to set foreground simulation mode: tclcommand="xschem netlist; simulate {xschem annotate_op}" In this case the annotation is given as callback argument to the simulate procedure. this callback will be scheduler after completion of the simulation, all in the background.

A caveat is that if you run the above set of commands you should not "walk away" from the schematic, otherwise the annotation will not work.

qpwo commented 7 months ago

What syntax is this callback from?

StefanSchippers commented 7 months ago

It is just an argument to the simulate procedure. In this case the argument is used as a command to run when simulation is completed.

qpwo commented 7 months ago

Ah ok that makes more sense

qpwo commented 7 months ago

Ah so I couldn't get it to work but it's my fault for using gnome-terminal. For example gnome-terminal -- sleep 1; echo done will echo done immediately. Will work it out on my own. Thank you for your help.