Intercompatibility with kicad 8

[Steffen-W]

          Hi @Steffen-W ,

I am having same error, but I thought it was because I'm using the version 8 release 3. I did not have any issues when using version 7.10. Just this file is having the issue. Here is the error I'm getting...

Any help solving the issue would be greatly appreciated as I use this tool often.

Thanks, Josh

Originally posted by @Joshc17m in https://github.com/Steffen-W/KiCad-Parasitics/issues/8#issuecomment-1961903674

[Steffen-W]

Hi @Joshc17m,

KiCad V7 .kicad_pcb

  (setup
    (stackup
      (layer "F.SilkS" (type "Top Silk Screen"))
      (layer "F.Paste" (type "Top Solder Paste"))
      (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
      (layer "F.Cu" (type "copper") (thickness 0.035))
      (layer "dielectric 1" (type "core") (thickness 1.5) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
      (layer "B.Cu" (type "copper") (thickness 0.035))
      (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
      (layer "B.Paste" (type "Bottom Solder Paste"))
      (layer "B.SilkS" (type "Bottom Silk Screen"))
      (copper_finish "None")
      (dielectric_constraints no)
    )

KiCad V8 .kicad_pcb

    (setup
        (stackup
            (layer "F.SilkS"
                (type "Top Silk Screen")
            )
            (layer "F.Paste"
                (type "Top Solder Paste")
            )
            (layer "F.Mask"
                (type "Top Solder Mask")
                (thickness 0.01)
            )
            (layer "F.Cu"
                (type "copper")
                (thickness 0.035)
            )
            (layer "dielectric 1"
                (type "core")
                (thickness 1.5)
                (material "FR4")
                (epsilon_r 4.5)
                (loss_tangent 0.02)
            )
            (layer "B.Cu"
                (type "copper")
                (thickness 0.035)
            )
            (layer "B.Mask"
                (type "Bottom Solder Mask")
                (thickness 0.01)
            )
            (layer "B.Paste"
                (type "Bottom Solder Paste")
            )
            (layer "B.SilkS"
                (type "Bottom Silk Screen")
            )
            (copper_finish "None")
            (dielectric_constraints no)
        )

Unfortunately, I did not set up the parser for the file properly. It is frustrating that changing the spaces can lead to it not working. Get_PCB_Stackup.py#L46

[Steffen-W]

Hi @Joshc17m, I have just tested it on my computer and it seems to work. can you send me your *.kicad_pcb? The first 150 lines of the file are relevant. You can also count the open and closed brackets in the file. It seems to me that the number is not the same.

[Joshc17m]

Hi @Steffen-W ,

Here is my first 156 lines....

(kicad_pcb (version 20240108) (generator "pcbnew") (generator_version "8.0") (general (thickness 1.7384) (legacy_teardrops no) ) (paper "A4") (title_block (title "IntelaLift") (date "2024-02-22") (rev "11") (company "Air Man") (comment 1 "DRWG BY: J. Christie") ) (layers (0 "F.Cu" signal) (1 "In1.Cu" power "GND.Cu") (2 "In2.Cu" power "POWER.Cu") (31 "B.Cu" signal) (32 "B.Adhes" user "B.Adhesive") (33 "F.Adhes" user "F.Adhesive") (34 "B.Paste" user) (35 "F.Paste" user) (36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen") (38 "B.Mask" user) (39 "F.Mask" user) (40 "Dwgs.User" user "User.Drawings") (41 "Cmts.User" user "User.Comments") (42 "Eco1.User" user "User.Eco1") (43 "Eco2.User" user "User.Eco2") (44 "Edge.Cuts" user) (45 "Margin" user) (46 "B.CrtYd" user "B.Courtyard") (47 "F.CrtYd" user "F.Courtyard") (48 "B.Fab" user) (49 "F.Fab" user) (50 "User.1" user) (51 "User.2" user) (52 "User.3" user) (53 "User.4" user) (54 "User.5" user) (55 "User.6" user) (56 "User.7" user) (57 "User.8" user) (58 "User.9" user) ) (setup (stackup (layer "F.SilkS" (type "Top Silk Screen") (color "White") ) (layer "F.Paste" (type "Top Solder Paste") ) (layer "F.Mask" (type "Top Solder Mask") (color "Blue") (thickness 0.01) ) (layer "F.Cu" (type "copper") (thickness 0.0696) ) (layer "dielectric 1" (type "prepreg") (color "FR4 natural") (thickness 0.1) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02) ) (layer "In1.Cu" (type "copper") (thickness 0.0696) ) (layer "dielectric 2" (type "core") (color "FR4 natural") (thickness 1.24) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02) ) (layer "In2.Cu" (type "copper") (thickness 0.0696) ) (layer "dielectric 3" (type "prepreg") (color "FR4 natural") (thickness 0.1) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02) ) (layer "B.Cu" (type "copper") (thickness 0.0696) ) (layer "B.Mask" (type "Bottom Solder Mask") (color "Blue") (thickness 0.01) ) (layer "B.Paste" (type "Bottom Solder Paste") ) (layer "B.SilkS" (type "Bottom Silk Screen") (color "White") ) (copper_finish "ENIG") (dielectric_constraints yes) ) (pad_to_mask_clearance 0) (allow_soldermask_bridges_in_footprints no) (pcbplotparams (layerselection 0x00010fc_ffffffff) (plot_on_all_layers_selection 0x0000000_00000000) (disableapertmacros no) (usegerberextensions no) (usegerberattributes yes) (usegerberadvancedattributes yes) (creategerberjobfile yes) (dashed_line_dash_ratio 12.000000) (dashed_line_gap_ratio 3.000000) (svgprecision 4) (plotframeref no) (viasonmask no) (mode 1) (useauxorigin no) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) (pdf_front_fp_property_popups yes) (pdf_back_fp_property_popups yes) (dxfpolygonmode yes) (dxfimperialunits yes) (dxfusepcbnewfont yes) (psnegative no) (psa4output no) (plotreference yes) (plotvalue yes) (plotfptext yes) (plotinvisibletext no) (sketchpadsonfab no) (subtractmaskfromsilk no) (outputformat 1) (mirror no) (drillshape 1) (scaleselection 1) (outputdirectory "") )

[Steffen-W]

Hi @Joshc17m,

Unfortunately, the problem does not seem to be there. Can you test the file test.kicad_pcb.txt and tell me if it works for you? Otherwise the problem will be somewhere else in the file. If possible, try to shorten the file so that the error still occurs. It would be helpful if you could send me the file.

[Steffen-W]

I assume that the problem has been solved.