The LPC bus code is emulating the basics of several components, including the MCPX ROM overlay. The ROM itself is mapped as a GPA range at the top of the x86 address space from 0xFF000000 to 0xFFFFFFFF and is manually filled up with bytes from the BIOS ROM. The last 512 bytes are replaced with the MCPX ROM if that is enabled. It is then restored once the disable bit is set.
The correct way to emulate this would be to attach devices to the LPC bus, one of them being the MCPX, and let MMIO flow through to the device in order to access the BIOS or MCPX ROM data depending on the state of the overlay. The GPA range reserved for the ROM would no longer be necessary.
The LPC bus code is emulating the basics of several components, including the MCPX ROM overlay. The ROM itself is mapped as a GPA range at the top of the x86 address space from 0xFF000000 to 0xFFFFFFFF and is manually filled up with bytes from the BIOS ROM. The last 512 bytes are replaced with the MCPX ROM if that is enabled. It is then restored once the disable bit is set.
The correct way to emulate this would be to attach devices to the LPC bus, one of them being the MCPX, and let MMIO flow through to the device in order to access the BIOS or MCPX ROM data depending on the state of the overlay. The GPA range reserved for the ROM would no longer be necessary.