As title suggests, this is not the entire X86 backend yet.
I spent a few days implementing the X86 backend and register allocation in parallel, so I could tweak the design and make sure I was in the right direction.
Note that my data representation is a strict subset of the real X86, but
it's expressive enough for producing a working program
it helped me make illegal state unrepresentable, e.g.,
parameterized instruction strictly separates code before and after register allocation
-Load and Store instead of Mov prevents multiple memory accesses in 1 instruction
As title suggests, this is not the entire X86 backend yet.
I spent a few days implementing the X86 backend and register allocation in parallel, so I could tweak the design and make sure I was in the right direction.
Note that my data representation is a strict subset of the real X86, but
LoadandStoreinstead ofMovprevents multiple memory accesses in 1 instruction