The STM32L0 LPTIM peripheral appears to trigger a match interrupt
whenever LPTIM_CMP >= LPTIM_CNT. Not only of LPTIM_CMP == LPTIM_CNT.
In most cases this works just fine: a timer interrupt is scheduled for t_future > t_now.
As soon as the counter hits t_future, the interrupt is raised as
expected.
However, this timer is just 16-bits, overflowing every 64 seconds
(assuming f = 1024 Hz). It is inevitable that the condition t_future < t_now happens
will happen at some point. As an example, what if t_now is close to 65536 and
we want to schedule an interrupt 1000 ticks in the future?
This patch works around this problem by checking that the timer is always
programmed with a CMP > CNT. If the new CMP value is smaller than the
current CNT value, the scheduling is handled from the overflow
interrupt: as soon as the overflow triggers, CMP > CNT(=0) by
definition.
The STM32L0 LPTIM peripheral appears to trigger a match interrupt whenever LPTIM_CMP >= LPTIM_CNT. Not only of LPTIM_CMP == LPTIM_CNT.
In most cases this works just fine: a timer interrupt is scheduled for t_future > t_now. As soon as the counter hits t_future, the interrupt is raised as expected.
However, this timer is just 16-bits, overflowing every 64 seconds (assuming f = 1024 Hz). It is inevitable that the condition
t_future < t_now happens
will happen at some point. As an example, what if t_now is close to 65536 and we want to schedule an interrupt 1000 ticks in the future?This patch works around this problem by checking that the timer is always programmed with a CMP > CNT. If the new CMP value is smaller than the current CNT value, the scheduling is handled from the overflow interrupt: as soon as the overflow triggers, CMP > CNT(=0) by definition.