"Resolution" of the I-V plots made with plotSys() changes with cell temperature

[adambgnr]

If I set the cell temperatures high, then the "resolution" of the I-V and Power plots made with plotSys() decreases: These 3 models have a uniform 1 suns of irradiance on them. The only difference is the cell temperatures indicated with colors.

[mikofski]

Hi @adambgnr

I have reproduced this issue, and I think I've traced the cause, but I'm still working on it.

In the meantime, there is a workaround. You can increase the resolution by creating a custom PVconstants instance with npts=1000

from pvmismatch import *
pvconst = pvconstants.PVconstants(npts=1000)
pvsys = pvsystem.PVsystem(pvconst=pvconst)
pvsys.setTemps(388)
f = pvsys.plotSys();
f.show()

[mikofski]

I traced the issue to pvconstants.calcSeries() specifically the lines that set the currents to interpolate voltage at - the minimum current in this example is HUGE (-589[A]), and I think it skews the interpolation.

https://github.com/SunPower/PVMismatch/blob/faca92f7d6036aca2564907224a8de5e3ad9e38a/pvmismatch/pvmismatch_lib/pvconstants.py#L139-L144

The resolution at the cell level is actually fine!

But the resolution problem starts at the module level, so that's what got me digging into pvmodule.PVmodule.CalcMod which calls pvconstants.calcSeries.

In the cell, the resolution is set in pvcell.PVcell.calcCell and I think the trouble starts with Vquad4 which is a range of diode voltages that try to ensure that there is sufficient coverage to interpolate cells of different temperatures:

https://github.com/SunPower/PVMismatch/blob/faca92f7d6036aca2564907224a8de5e3ad9e38a/pvmismatch/pvmismatch_lib/pvcell.py#L214-L230

The issue, I believe is that although the diode voltage is set to Voc at STC, this results in a cell voltage that is much larger! EG:

>>> pvsys_pvstr0 = pvsys.pvstrs[0]  # first string (str-0)
>>> pvsys_pvstr0_pvmod0 = pvsys_pvstr0.pvmods[0]  # first module (mod-0. str-0)
>>> pvsys_pvstr0_pvmod0.pvcells[0].VocSTC  # Voc@STC of first cell in (mod-0, str-0)
0.6744401939866893  # upper limit used in Vquad4

>>> pvsys_pvstr0_pvmod0.pvcells[0].Vcell[-1]  # last point in I-V curve for (cell-0, mod-0, str-0)
array([3.18693553])

>>> pvsys_pvstr0_pvmod0.pvcells[0].Icell[-1]  # last point in I-V curve for (cell-0, mod-0, str-0)
array([-588.78742012])

>>> pvsys_pvstr0_pvmod0.pvcells[0].Rs  # series resistance
0.004267236774264931

>>> pvsys_pvstr0_pvmod0.pvcells[0].Rs * pvsys_pvstr0_pvmod0.pvcells[0].Icell[-1]
... + pvsys_pvstr0_pvmod0.pvcells[0].Vcell[-1]
array([0.67444019])  # Vdiode = Vcell + Icell * Rs

So you can see that the setting the diode voltage to the estimated Voc at STC does accomplish the goal of being well into the 4th quadrant, it's TOO FAR! And that results in a minimum current, Imin in the pvconstants.calcSeries(), that is TOO BIG!

[mikofski]

I can confirm that Imin is the culprit. If I simple set Imin to zero, then the issue is resolved for the specific example I used in this issue, but I wonder if there are any edge cases I need to consider?

OK, I have talked to the master (@jdnewmil) and he reminded me of 2 things:

1. I am frequently asked what if there is negative current in the string, so the answer to my question about edge cases is yes, and I propose we do the same thing we do for voltage in the cell, and divide the current into 3 regions: reverse, forward, and negative (or quad4)
2. We better check that pvconstants.calcParallel() also works correctly too, because if this problem exists for series cells, then it might for cross-ties as well.

[mikofski]

PR #112 seems to be working, but there are still a few tests I need to fix firsts, and there's an issue with cross-tied (aka: shingled or tilted) modules.