Closed quietboil closed 5 years ago
This might be a problem as an 8 bit access to iram generates a load exception, very slow, and perhaps some code will expected gpio access to be fast. So it might be best to either revert this, or change it to place these in data RAM?
an 8 bit access to iram generates a load exception
Agree. My fault. I managed to miss the section attribute on those arrays :disappointed:
Reverted
Both maps are in RAM, so there is really no need to allocate extra memory for each entry - no aligned reads.
The assembler for
gpio_to_iomux
andiomux_to_gpio
differs only in how array entry address (offset) is calculated:addx4 a2, a2, a3
add.n a2, a3, a2