There is a lack of testing around some key portions of the FPGA interchange implementation. There is also some key performance issues that prevent the implementation from being particularly usable.
Get FPGA interchange 7-series nextpnr implementation to feature parity with symbiflow-arch-defs
Many important features present in the symbiflow-arch-defs are missing from the currently FPGA interchange flow. Significant work remains to reach feature parity.
Start testing more circuits (some may be blocked by CARRY4/LUT-RAM implementations)
Get FPGA interchange nextpnr implementation to bigger fabrics and circuits
The current 7-series and other initial target architectures are limited to the 50k - 200k LUT range. To test with larger design, UltraScale+ (or other) fabrics will need to be supported. This category of work covers what is required to being to explore working with larger and larger fabrics, with the end goal of operating on the largest fabrics from Xilinx (VU19P) and other vendors.
UltraScale+ bring-up (Ultra96 / UltraScale+ MPSoC ZU3EG) (Put link to issue here!)
Project page: https://github.com/orgs/SymbiFlow/projects/22
The implementation of the FPGA interchange as of https://github.com/YosysHQ/nextpnr/commit/692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3 and https://github.com/SymbiFlow/python-fpga-interchange/commit/b4331eff339790b9eaa095083aec5e628712bb75 can place and route 7-series designs using single ended IO, FF's, LUT's and BRAM's for the most part. This issue covers the remaining work in different directions that the FPGA interchange development can take from here. I've broadly broken future work into 3 area's of work.
Improvement testing, robustness and speed
There is a lack of testing around some key portions of the FPGA interchange implementation. There is also some key performance issues that prevent the implementation from being particularly usable.
Get FPGA interchange 7-series nextpnr implementation to feature parity with symbiflow-arch-defs
Many important features present in the symbiflow-arch-defs are missing from the currently FPGA interchange flow. Significant work remains to reach feature parity.
Get FPGA interchange nextpnr implementation to bigger fabrics and circuits
The current 7-series and other initial target architectures are limited to the 50k - 200k LUT range. To test with larger design, UltraScale+ (or other) fabrics will need to be supported. This category of work covers what is required to being to explore working with larger and larger fabrics, with the end goal of operating on the largest fabrics from Xilinx (VU19P) and other vendors.