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SymbiFlow / vtr-verilog-to-routing

SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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DNM: Test removing std::isfinite check from timing_util. #426

Closed litghost closed 4 years ago

litghost commented 4 years ago

This was added long ago, and may no longer be required. This PR is to test if this modification can be removed!