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SymbiFlow / vtr-verilog-to-routing

SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Master+wip next #560

Closed HackerFoo closed 3 years ago

HackerFoo commented 3 years ago

Update master+wip to include https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1586

litghost commented 3 years ago

I think you ran update_tools.py a couple times over a dirty output directory? For example, I see some file conflicts that got commited: CMakeLists.txt.orig and CMakeLists.txt.rej

I believe if you point the tool at an empty folder those kinds of issue don't crop up.

litghost commented 3 years ago

I also see some new files that I don't think came from upstream, e.g. default.nix

litghost commented 3 years ago

Merging this as is for now. Once https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1576 we should be able to drop the remaining wip/ branches (connection box and update_golden).