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SymbiFlow / yosys

SymbiFlow WIP changes for Yosys Open SYnthesis Suite
http://www.clifford.at/yosys/
ISC License
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Yosys cannot infer BRAM correctly on current master+wip #17

Closed mkurc-ant closed 5 years ago

mkurc-ant commented 5 years ago

Yosys on current master+wip (SHA: 22eaab1) cannot infer BRAM (or any memory) when given a verilog array with a series of initial statements.

I've checked that the last correctly working commit is 98104b3.

In order to reporoduce:

  1. Clone the Yosys repo (master+wip branch)
  2. Build it
  3. Set env. variable YOSYS to point to the Yosys binaty
  4. Clode the symbiflow-arch-defs repo (master 2e7d736) and run make env
  5. Build EBLIF file for tests/9-soc/picosoc
  6. Check how many BRAMS are there in the synthesized design. There should be 2 instead of 1.

I don't know if it is an upstream bug or not so I am posting it here.

mkurc-ant commented 5 years ago

This PR in YosysHQ introduced the unwanted behavior: https://github.com/YosysHQ/yosys/pull/843

mkurc-ant commented 5 years ago

Created an issue upstream: https://github.com/YosysHQ/yosys/issues/867

mkurc-ant commented 5 years ago

So the problem is now fixed on YosysHQ (f0b2d8e). @litghost Can you integrate master+wip from YosysHQ again? Or at least changes from https://github.com/YosysHQ/yosys/pull/868

litghost commented 5 years ago

So the problem is now fixed on YosysHQ (f0b2d8e). @litghost Can you integrate master+wip from YosysHQ again? Or at least changes from YosysHQ#868

I can, but FYI you could have also made the PR.

mkurc-ant commented 5 years ago

@litghost Ok, I've created a PR: https://github.com/SymbiFlow/yosys/pull/19