search

SymbiFlow / yosys

SymbiFlow WIP changes for Yosys Open SYnthesis Suite
http://www.clifford.at/yosys/
ISC License
37 stars 9 forks source link

Branch: Quicklogic : Yosys optimizes the design completely when no IO's/ PADs defined in the design #62

Closed rakeshm75 closed 4 years ago

rakeshm75 commented 4 years ago

Steps to reproduce the issue

  1. Synthesize any design without IO pads using yosys

IP designs on S3 devices can be used for processing data within S3, without external IO defined in the IP design. S3 has ASSP block (M4) which interfaces with the FPGA block, so there could be design where M4 sends data to FPGA, FPGA IP (like FFT) process the data and sends it back to M4. No external IO, in the FPGA IP, need to be defined in these scenario.

But Yosys, completely optimizes the design when it does not see any IO defined in the FPGA design. Test_Design2.zip

glatosinski commented 4 years ago

I updated https://github.com/antmicro/yosys/tree/quicklogic fork, where the support for QuickLogic devices currently resides. Now the qlal4s3b_cell_macro module has attribute keep that will preserve this cell, and communication with it.

GitHub
antmicro/yosys
Yosys Open SYnthesis Suite. Contribute to antmicro/yosys development by creating an account on GitHub.
rakeshm75 commented 4 years ago

The issue is fixed. So closing the issue.

Thanks & Best Regards, Rakesh