Branch: Quicklogic : Functional issue in the design with Yosys generated edf

[rakeshm75]

Steps to reproduce the issue

1. Run the attached design through Yosys flow - works fine
2. Run PNR of the EDF file created by Yosys on SpDE - works fine
3. Run Simulation - Fails
4. Run the FPGA register access test on the board - fails

Expected behavior

write the register (0x40020804) = 0x87F Read the register (0x40020804) expected result = 0x87B

Actual behavior

write the register (0x40020804) = 0x87F Read the register (0x40020804) actual result = 0x873

Please describe how the behavior you see differs from the expected behavior. We see the bit[3] of the register (which is RX FIFO Full Interrupt Enable) = 0 even though it is set to 1.

one observation: In this design there is a register bit which has the asynchronous set and Async reset, if I change that register to remove the async set then the register access works fine.

"always @( posedge WBs_CLK_i or posedge WBs_RST_i or posedge DMA_done_i) begin if (WBs_RST_i) begin DMA_Done_IRQ <= 1'b0; end Test_design9.zip Test_design9.zip

else if (DMA_done_i)
    DMA_Done_IRQ             <= 1'b1;
else
begin
    if ( (VGA_DMA_CTRL_Wr_Dcd && WBs_BYTE_STB_i[0]))
    begin
       DMA_Done_IRQ   <=  WBs_DAT_i[2];
    end
end  

end "

[glatosinski]

We've updated the flip flop implementations - could you please check now how if the design works for you? Please use quicklogic-rebased branch for https://github.com/antmicro/yosys repository

GitHub

antmicro/yosys

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