RVFIMON generate.py not creating ialign16

SymbioticEDA / riscv-formal

RISC-V Formal Verification Framework

ISC License

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RVFIMON generate.py not creating ialign16 #30

Open jasonB221 opened 5 years ago

jasonB221 commented 5 years ago

When running monitor/generate.py with default arguments, wire ialign16 is not generated in the output of any instruction module. It appears that print_rewritefile cannot handle the nested `ifdefs present in the various insn*.v files.

jleahy commented 5 years ago

I think I've fixed this in PR #31