It turns out that currently generate.py produces invalid Verilog for RV32I (C extension disabled), particularly you end up with ialign16 not getting defined. This is because some instructions (such as BEQ) have nested ifdefs that aren't handled by the parser. I've extended it to track a stack of ifdefs instead. This also cuts down the lines of code a little and makes it easier to extend for additional flags.
The other two changes are just niceties whilst I was in the vicinity.
Hi Clifford,
It turns out that currently generate.py produces invalid Verilog for RV32I (C extension disabled), particularly you end up with
ialign16not getting defined. This is because some instructions (such as BEQ) have nested ifdefs that aren't handled by the parser. I've extended it to track a stack of ifdefs instead. This also cuts down the lines of code a little and makes it easier to extend for additional flags.The other two changes are just niceties whilst I was in the vicinity.