Open Freedom-is-slavery opened 2 years ago
I'm not an expert in RDL, but the RDL spec on page 80 has an example of overriding this, and it uses parameters. Maybe try that?
Just wanted to post here that I did not forget about this issue.
I'm planning a significant refactor of the UVM generator (see issues tagged in v3.0
milestone), and plan to address this then.
Hi, I write SystemRDL like this:
where
test_map_3_inst
is a addrmap component instance. The question is, as you can see, I dynamically assign a hdl_path property totest_map_3_inst
, but in generated UVM RAL model, the hdl_path is not generated:It seems like only register components with hdl_path properties results in a add_hdl_path_slice() function call, like this:
where
shared_3
is areg
component instance, and generated UVM RAL:Being not familiar with UVM, in my opinion, ultimately all
hdl_path
in different hierarchies will be concatenated for RTL design verification. Is there some special consideration about thehdl_path
property assigned in different components?