generate verilog file, not system verilog.

SystemRDL / PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input

GNU General Public License v3.0

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generate verilog file, not system verilog. #30

Open yqdvan opened 4 months ago

yqdvan commented 4 months ago

Your code is very impressive, but could you please tell me how to generate Verilog files?

amykyta3 commented 4 months ago

The official PeakRDL project does not have any Verilog-2005 generators. However there are some community projects that may be able to suppport the older versions of the language. I noticed this one exists: https://github.com/hughjackson/PeakRDL-verilog

yqdvan commented 4 months ago

thanks for your reply， kind regards！发自我的 iPhone

在 2024年2月2日，15:26，Alex Mykyta @.***> 写道：

The official PeakRDL project does not have any Verilog-2005 generators. However there are some community projects that may be able to suppport the older versions of the language. I noticed this one exists: https://github.com/hughjackson/PeakRDL-verilog