SystemRDL / PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input
GNU General Public License v3.0
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Print the UVM RAL data, with MSB bits first #6

Closed muneebullashariff closed 4 years ago

muneebullashariff commented 4 years ago

Currently, the generated UVM RAL data fields are as follows:

msb_bits

Could you please provide a switch(MSB first) so that the display is as below: rand uvm_reg_field MTR3; rand uvm_reg_field MTR2; rand uvm_reg_field MTR1; rand uvm_reg_field MTR0;

muneebullashariff commented 4 years ago

I have fixed this by using the below code in uvm_reg.sv

{% for field in node.fields()|reverse -%}