[FEATURE] Add logic that represents an entire register and not just fields

[ronke10]

Describe the problem/limitation you think should be addressed Inability to view an entire register as a vector during the design verification process with tools such as Verdi, SimVision etc... Since registers are constructed as structs, the current approach restricts the tracking to individual fields rather than the complete register value.

I often need to monitor multiple registers concurrently, which currently necessitates tracking each field of every register independently. Solving this problem would improve the efficiency, simplicity, and convenience of the verification process.

Describe the solution you'd like Implementing a mechanism that represents the entirety of a register. For example, adding a logic that represents an entire register.

Thank you for this great work!

[amykyta3]

Thanks for your comment. Unfortunately this is not something that aligns well with the philosophy of this project. PeakRDL-regblock is intended to be an abstraction away from the hardware structure, so aside from how fields are addressed within a register from the CPU interface, the actual bit-layout of a register is not intended to ever be preserved in the hardware. To build in such a feature would be quite cumbersome.

This is also consistent with SystemRDL's modeling of memory maps - that registers are conceptual containers for the actual physical elements that are fields. Verification libraries like UVM use a similar approach.