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TENNLab-UTK / fpga

FPGA neuromorphic elements, networks, processors, tooling, and software interfaces.
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In SISO mode, AXIS master tvalid signal is uneffected when AXIS slave tready signal goes low. #11

Closed BGull00 closed 2 months ago

BGull00 commented 2 months ago

When Stream-In-Stream-Out (SISO) mode is used and input data is being streamed in more quickly than the neuro FPGA can handle, backpressure occurs and the AXIS slave tready signal goes low. The valid signals inside of the neuro FPGA are uneffected by this backpressure / tready falling. This becomes a problem as the AXIS master tvalid signal stays high, which causes the AXIS master channel to transfer invalid data (or repeatedly send data by mistake). In the case of SISO, where we would normally expect one incoming data transfer to yield one outgoing data transfer, one incoming data transfer can mistakenly yield more than one outgoing data transfer. This is highlighted by the simulated waveforms attached to this Issue. Notice that AXIS master tvalid stays high even when AXIS slave tready repeatedly goes low.

Screenshot from 2024-08-05 17-00-29

keegandent commented 2 months ago

Not sure if you saw me tag you in a commit message, but I pushed changes to the bug-stream-source-tvalid-not-reset branch that work in UART SISO and SIDO, so let me know how that does on your bench please

BGull00 commented 2 months ago

This looks like it's fixed now on my end. Although, I'm going to test it more thoroughly here in the next few days with more data and a few different networks.

keegandent commented 2 months ago

This looks like it's fixed now on my end. Although, I'm going to test it more thoroughly here in the next few days with more data and a few different networks.

Opened the PR, but feel free to wait until you're more certain we squashed the bug.

keegandent commented 2 months ago

@BGull00, would you mind testing stream-source-one-cycle-processing as well? In theory, it should also fix the issue but have double the data rate. I think I cracked creating a half-clock reset pulse which lets us CLR and SPK in one clock cycle, but maybe I'm crazy and it breaks for fast sources and sinks. It would solve #4.

keegandent commented 2 months ago

@BGull00 updated both the bugfix and one-cycle branch with main. I suggest pulling main with a rebase, then testing that branch to see if everything still works with DMA at an improved data rate.