One of the parameters called out in #20. The FPGA RISP Processor currently does not support fire_like_ravens set to true. This narrows the ability to test RISP networks which could otherwise perhaps easily be migrated to RAVENS.
Proposed Solution
From my observation, this should be achievable by making fire from a wire (combinational logic) into a register (flip-flop logic) when the FIRE_LIKE_RAVENS parameter is true.
Hurdles
Important to note that neuron potential resetting should not depend on the value of the fire flip-flop, but rather the input. will_fire or fire_cond might be good names for such a wire.
Expected API Impacts
This should create a compatibility improvement for the fpga.Processor.load_network() function.
Problem
One of the parameters called out in #20. The FPGA RISP Processor currently does not support
fire_like_ravens
set totrue
. This narrows the ability to test RISP networks which could otherwise perhaps easily be migrated to RAVENS.Proposed Solution
From my observation, this should be achievable by making
fire
from a wire (combinational logic) into a register (flip-flop logic) when theFIRE_LIKE_RAVENS
parameter is true.Hurdles
Important to note that neuron potential resetting should not depend on the value of the
fire
flip-flop, but rather the input.will_fire
orfire_cond
might be good names for such a wire.Expected API Impacts
This should create a compatibility improvement for the
fpga.Processor.load_network()
function.