Our SystemVerilog parameterized interface structures, while making the code neater, are causing development pains in other ways. Most importantly, Quartus will not synthesize any code which references the value of interface parameters as an assignment to a constant value (parameter, localparam, etc.)
Proposed Solution
Based on discussion in #26, we are moving to a more verbose All-Verilog implementation of AXIS components.
Hurdles
There have been issues previously implementing the AXIS UART to AXIS Adapter connection, related to tkeep, but I believe that was resolved in https://github.com/alexforencich/verilog-axis/issues/32. It may also be worth running uart-loopback again to make sure the supported baud rates don't change.
Problem
Our SystemVerilog parameterized
interfacestructures, while making the code neater, are causing development pains in other ways. Most importantly, Quartus will not synthesize any code which references the value of interface parameters as an assignment to a constant value (parameter,localparam, etc.)Proposed Solution
Based on discussion in #26, we are moving to a more verbose All-Verilog implementation of AXIS components.
Hurdles
There have been issues previously implementing the AXIS UART to AXIS Adapter connection, related to
tkeep, but I believe that was resolved in https://github.com/alexforencich/verilog-axis/issues/32. It may also be worth runninguart-loopbackagain to make sure the supported baud rates don't change.Expected API Impacts
Ideally this will have no impacts.