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TENNLab-UTK / fpga

FPGA neuromorphic elements, networks, processors, tooling, and software interfaces.
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Neurons without incoming synapses that are on a path from an input neuron are handled erroneously in hardware #33

Open BGull00 opened 6 days ago

BGull00 commented 6 days ago

Neurons without incoming synapses that are on a path from an input neuron are not properly handled in the generated network SystemVerilog file. This causes signals to go to an undetermined state (symbolized by the dreaded X in Vivado's sim). For example, an output neuron with no incoming synapses is declared by logic signed [NET_CHARGE_WIDTH-1:0] neur_95_inp [0:-1]; and neur_95_inp is not assigned anywhere (as there is no input to the neuron). In this case, the neur_95_inp array should be of size 1 (i.e. neur_95_inp[0:0]), and the only array value should be directly connected to logic value 0.

BGull00 commented 6 days ago

This also needs fixing inside of the neuron SystemVerilog file as NUM_INP can be equal to 0. This same bug of doing logic [NUM_<something>-1:0] when NUM_<something> could be 0 could exist elsewhere in the code base and lead to more future issues.

keegandent commented 6 days ago

So my understanding is these neurons existing in the network graph only makes sense if we agree that for #32, neurons with threshold + !threshold_inclusive <= 0 should spike every run unless they receive inhibitory input.