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TENNLab-UTK / fpga

FPGA neuromorphic elements, networks, processors, tooling, and software interfaces.
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Networks and Input Spike Rasters for Integration Testing #34

Open keegandent opened 3 weeks ago

keegandent commented 3 weeks ago

Problem

Issues like #30 and #32 are likely to continue lurking without some better example networks to verify behavior in simulation and HWIL.

Proposed Solution

Select some FPGA-compatible RISP networks. Provide a set of testing input spike and run calls that exercise as much of the network behavior as possible. There's no need to provide known output rasters, as the test scripts can use the simulator at test-time to validate results.

Hurdles

Many if not most of the simulator networks are floating-point?

Expected API Impacts

None.

keegandent commented 3 weeks ago

@BGull00, @charizzo, @aweis-9535 could one or two of you please take this?

aweis-9535 commented 3 weeks ago

I can definitely take this; I'll need someone else to help with defining the RISP network.

keegandent commented 3 weeks ago

I can definitely take this; I'll need someone else to help with defining the RISP network.

@charizzo would that be you?