Add a generic upscale and downscale module and allow for variable width interfaces with it.
For slow transports like UART they probably are just added to the interface behind all FIFOs, for fast ones upscaling should happen between the IO line speed and the buffers.
Add a generic upscale and downscale module and allow for variable width interfaces with it.
For slow transports like UART they probably are just added to the interface behind all FIFOs, for fast ones upscaling should happen between the IO line speed and the buffers.