WIP: Uart ingress buffer ordering - Githubissues

TUM-LIS / glip

Generic Logic Interfacing Project

http://glip.io

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WIP: Uart ingress buffer ordering #33

Closed imphil closed 7 years ago

imphil commented 7 years ago

This is not yet ready to be merged

This PR changes the ordering of the modules in the UART ingress and egress paths to improve the overall timing when used in other projects.

What works:

loopback demo on Nexys 4 DDR

What does not work:

loopback demo on VCU 108

TODO:

Figure out what goes wrong on the VCU108. Earlier tests showed that the ingress data path most likely is ok, but the egress data path has a bug. Since in the egress path no modules were reordered but just signals are renamed, it's most likely just a forgotten signal/misnamed port, etc.