gem5-SALAM build error after creating a new SimObject

[mhezarei]

Greetings, hope you are doing well.

Using the most updated version of gem5-SALAM repo, I get a weird "undefined reference" error while building gem5-SALAM after creating a simple SimObject under the hwacc directory. This did not use to be the case using the older versions of gem5-SALAM.

Classes I'm defining:

# hwacc/Temp.py

from m5.params import *
from m5.proxy import *
from m5.objects.Device import BasicPioDevice

class Temp(BasicPioDevice):
    type = "Temp"
    cxx_header = "hwacc/temp.hh"

    devicename = Param.String("temp", "Device name")

// hwacc/temp.hh

#ifndef __HWACC_TEMP_HH__
#define __HWACC_TEMP_HH__

#include "dev/io_device.hh"
#include "params/Temp.hh"

#include <queue>
#include <vector>

class Temp : public gem5::BasicPioDevice {
private:
  std::string deviceName;

public:
  Temp(const gem5::TempParams &p);
};

#endif // __HWACC_TEMP_HH__

// hwacc/temp.cc

#include "hwacc/temp.hh"
#include "base/trace.hh"
#include "sim/system.hh"

#include <string>

Temp::Temp(const gem5::TempParams &p)
    : BasicPioDevice(p, 0), deviceName(p.devicename) {}

The error I get while building gem5-SALAM (happens in the [ LINK] -> ARM/gem5.opt step):

/usr/bin/ld: build/ARM/python/_m5/param_Temp.o: in function `gem5::module_init(pybind11::module_&)':
<gem5-SALAM>/build/ARM/python/_m5/param_Temp.cc:32: undefined reference to `gem5::TempParams::create() const'
clang: error: linker command failed with exit code 1 (use -v to see invocation)

Thanks in advance!

[zephan-spencer]

Did you add it to scons? It looks like it just never built the simobject

[mhezarei]

Yes. Here is what hwacc/SConscript looks like (Asterisks before the newly added lines). As I said, I have done this a handful of times now, and this has never been the case.

Import('*')

if env['TARGET_ISA'] == 'arm':

    #Example
    #SimObject('IOAcc.py')

    #CommInterface
    SimObject('CommInterface.py')
    SimObject('ScratchpadMemory.py')
    SimObject('NoncoherentDma.py')
    SimObject('StreamDma.py')
    SimObject('AccCluster.py')
    SimObject('StreamBuffer.py')
    SimObject('RegisterBank.py')

    #LLVMInterface
    SimObject('ComputeUnit.py')
    SimObject('LLVMInterface.py')

    #HWInterface
    SimObject('CycleCounts.py')
    SimObject('FunctionalUnits.py')
    SimObject('HWInterface.py')
    SimObject('HWStatistics.py')
    SimObject('InstConfig.py')
    SimObject('InstOpCodes.py')
    SimObject('SALAMPowerModel.py')
    SimObject('SimulatorConfig.py')

    #Custom Objects
    ********** SimObject("Temp.py")

    #Functional Units
    #SimObject('Adder.py')

    # 
    Source('comm_interface.cc')
    Source('compute_unit.cc')
    Source('llvm_interface.cc')
    Source('dma_write_fifo.cc')
    Source('noncoherent_dma.cc')
    Source('stream_dma.cc')
    Source('acc_cluster.cc')
    Source('stream_buffer.cc')
    Source('stream_port.cc')
    Source('scratchpad_memory.cc')
    Source('register_bank.cc')
    ********** Source('temp.cc')

    #
    Source('LLVMRead/src/value.cc')
    Source('LLVMRead/src/function.cc')
    Source('LLVMRead/src/basic_block.cc')
    Source('LLVMRead/src/debug_flags.cc')
    Source('LLVMRead/src/mem_request.cc')
    Source('LLVMRead/src/instruction.cc')
    Source('LLVMRead/src/registers.cc')
    Source('LLVMRead/src/operand.cc')

    # GENERATED FILES
    # Source('HWModeling/generated/functionalunits/adder.cc')
    # Source('HWModeling/generated/instructions/add.cc')
    # END OF GENERATED FILES

    Source('HWModeling/src/cycle_counts.cc')
    #Source('HWModeling/src/cacti_wrapper.cc') 
    Source('HWModeling/src/functional_units.cc')
    Source('HWModeling/src/hw_interface.cc')
    Source('HWModeling/src/hw_statistics.cc')
    Source('HWModeling/src/instruction_config.cc')
    Source('HWModeling/src/opcodes.cc')
    Source('HWModeling/src/salam_power_model.cc')
    Source('HWModeling/src/simulator_config.cc')

    #
    DebugFlag('CommInterface')
    DebugFlag('CommInterfaceQueues')
    DebugFlag('DeviceMMR')
    DebugFlag('LLVMInterface')
    DebugFlag('NoncoherentDma')
    DebugFlag('LLVMParse')
    DebugFlag('Runtime')
    DebugFlag('RuntimeCompute')
    DebugFlag('RuntimeQueues')
    DebugFlag('SALAM_Debug')
    DebugFlag('StreamBuffer')
    DebugFlag('StreamDma')
    DebugFlag('Trace')
    DebugFlag('Step')

    #
    CompoundFlag('JDEV', ['LLVMInterface','CommInterface', 'Runtime', 'RuntimeCompute', 'RuntimeQueues', 'SALAM_Debug'])
    CompoundFlag('HWACC', ['CommInterface', 'LLVMInterface'])

[mhezarei]

Fixed the issue by adding the MMR read/write requirements listed below:

1. SimObject class attributes: Addr io_size, Addr io_addr, uint8_t *mmr, ByteOrder endian, RequestorID masterId
2. SimObject functions: virtual Tick read(PacketPtr pkt), virtual Tick write(PacketPtr pkt). Implementation for these two could be copied from comm_interface.cc

[zephan-spencer]

Thanks for the solution, sorry I forgot to get back to this.