I am learning the use of VOSS2, and I tried to write a very simple STE code for Memory testing.
For this Memory, write at time 1 and read at time 2.
But the result of symbolic simulation of output singal "io_dataOut" at moment 2 is X, I don't know where is my problem?
Below is the verilog code
module mem(
input clock,
input [31:0] io_dataIn,
output [31:0] io_dataOut,
input [4:0] io_addr,
input csen_n,
input wren_n
);
reg [31:0] mem [4:0];
always @(posedge clock) begin
if(wren_n && !csen_n)
mem[io_addr] <= io_dataIn;
end
always @(posedge clock) begin
if(!wren_n && !csen_n)
io_dataOut <= mem[io_addr];
end
endmodule
Below is the fl code
load "ste.fl";
let p = verilog2pexlif F ("-I"^DIR^"") "mem" ["mem.v"] [];
let ckt = pexlif2fsm p;
let ant =
"clock" is_clock 2 and
"csen_n" is 0 for 2 cycles and
"wren_n" is 1 for 1 cycle followed_by //write at one cycle
0 for 1 cycle //read at second cycle
and
"io_addr[4:0]" is 2 for 2 cycles //write/read for addr-2
and
"io_dataIn[31:0]" is 4 for 2 cycles //write_data is 4
;
let vis = STE_debug ckt;
let ste = STE "-e" vis [] ant [] [];
ste;
Below is the waveform diagram of symbolic simulation
I am learning the use of VOSS2, and I tried to write a very simple STE code for Memory testing. For this Memory, write at time 1 and read at time 2. But the result of symbolic simulation of output singal "io_dataOut" at moment 2 is X, I don't know where is my problem?