Hello,
I am currently running Voss on a machine with Ubuntu 23.04. I have had success with creating circuits using the fl programming language, but when trying to convert Verilog code, I recieve an error saying Yosys failed, although I have installed oss-cad-suite and added it to my path. I have followed the example provided in the "Getting Started With VossII and Fl" Guide. I will attach a screenshot of my output.
Also, this is unrelated to my issue, but is there anyway to copy and paste into the fl terminal? It would make things a bit easier when one encounters an error and wishes to change their code.
Hello, I am currently running Voss on a machine with Ubuntu 23.04. I have had success with creating circuits using the fl programming language, but when trying to convert Verilog code, I recieve an error saying Yosys failed, although I have installed oss-cad-suite and added it to my path. I have followed the example provided in the "Getting Started With VossII and Fl" Guide. I will attach a screenshot of my output.
Also, this is unrelated to my issue, but is there anyway to copy and paste into the fl terminal? It would make things a bit easier when one encounters an error and wishes to change their code.
Thank you