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ThalesGroup / cva6-softcore-contest

National RISC-V student contest CV32A6
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Bump verif/core-v-verif from `6779193` to `d4e32fc` #31

Closed dependabot[bot] closed 7 months ago

dependabot[bot] commented 7 months ago

Bumps verif/core-v-verif from 6779193 to d4e32fc.

Commits
  • d4e32fc Merge pull request #2413 from MarioOpenHWGroup/fix/tandem-requirements-for-vcs
  • fc7ba9e Use IMPERAS as default ISS
  • f0a1ec9 Add VCS support for riscv-isa-sim tandem
  • f7bda8e Merge pull request #2409 from ludovicpion/master
  • 8b07974 remove artificial layer of heirarchy (bp_gen/bp_gen). It was a mistake
  • ba443fb remove artificial layer of heirarchy (bp_gen/bp_gen). It was a mistake
  • 31bcffe Changes to reply to issue #2403, #2407 and #2408
  • bbbd3b8 Merge pull request #2406 from ThalesSiliconSecurity/fix/vptool-example
  • c3051a6 [VPTOOL] Add copyright comments to VPTOOL example DB files.
  • a43cb94 [VPTOOL] Move "#!" interpreter line to correct location in vptool.sh.
  • Additional commits viewable in compare view


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dependabot[bot] commented 7 months ago

The following labels could not be found: Component:Verif.

dependabot[bot] commented 7 months ago

Superseded by #32.