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ThalesGroup / cva6-softcore-contest

National RISC-V student contest CV32A6
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Bump verif/core-v-verif from `6779193` to `b92d30f` #36

Closed dependabot[bot] closed 5 months ago

dependabot[bot] commented 5 months ago

Bumps verif/core-v-verif from 6779193 to b92d30f.

Commits
  • b92d30f Merge pull request #2416 from ThalesSiliconSecurity/AXISlave_Agent
  • c01247b axi_agent: new AXI agent transaction based
  • 416fddc Merge pull request #2452 from MarioOpenHWGroup/2450/fix-env-variables
  • 0036e69 LIBS on gen_corev-dv
  • 7f5193e export ${SIM}_HOME variables for riscv-isa-sim
  • 4a70806 Merge pull request #2412 from MarioOpenHWGroup/feature/more-tandem-params-and...
  • 9d113fa Rename patch
  • 730e090 Many fix for riscv-isa-sim
  • 399438e Merge pull request #2424 from xiaoweish/add-support-to-B-ext
  • 4e6e860 Merge pull request #2442 from ThalesSiliconSecurity/fix/spike-version-reporting
  • Additional commits viewable in compare view


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dependabot[bot] commented 5 months ago

The following labels could not be found: Component:Verif.

dependabot[bot] commented 5 months ago

Superseded by #37.