OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
In libs.tech/openlane/config.tcl following configuration should be updated.
set ::env(GPIO_PADS_VERILOG) "\
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v\
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v\
"
Because $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v file path not exist and sky130_ef_io__gpiov2_pad_wrapped module as part of sky130_ef_io.v
Following configuration will resolve the issues of missing file path:
set ::env(GPIO_PADS_VERILOG) "\
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v\
"
Logs
2. Executing Verilog-2005 frontend: /home/vijayan/MPW_CI/OpenLane-MPW-CI/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
ERROR: Can't open input file `/home/vijayan/MPW_CI/OpenLane-MPW-CI/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v' for reading: No such file or directory
child process exited abnormally
Description
In
libs.tech/openlane/config.tcl
following configuration should be updated.Because
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v
file path not exist andsky130_ef_io__gpiov2_pad_wrapped
module as part ofsky130_ef_io.v
Environment
Reproduction Material
Following MPW shuttle design will re-produce this error: https://github.com/shalan/Caravel_Chameleon_SoC/blob/master/openlane/chip_io/config.tcl
Quick check in PDK path:
Expected behavior
Following configuration will resolve the issues of missing file path:
Logs