Closed akifcelik closed 2 years ago
@akifcelik Have you tried with latest OpenLane git version?
For synthesis issue, you have to provide ALU/src
RTL files and config.tcl
to debug the issue.
Hi, I have run again with different directory but result unchanged and failed in synthesize. I have checked following command whether openlane is last version. answer is yes. akif@DESKTOP-FA8IJ3J:~/OpenLane$ git checkout master Already on 'master' Your branch is up to date with 'origin/master'. akif@DESKTOP-FA8IJ3J:~/OpenLane$
Project folder with verilog and config.tcl files: Non_storing_divider.zip
@akifcelik
Update config.tcl
with set ::env(SYNTH_STRATEGY) {DELAY 1}
will pass synthesis stage
@vijayank88 Hi ,it has also worked with set ::env(SYNTH_STRATEGY) {AREA 3} .thank you for supporting.
Hi , ı have latest Openlane version. I have attached project files to comment on github as a reply.
vijayan @.***>, 29 Haz 2022 Çar, 08:13 tarihinde şunu yazdı:
@akifcelik https://github.com/akifcelik Have you tried with latest OpenLane git version?
— Reply to this email directly, view it on GitHub https://github.com/The-OpenROAD-Project/OpenLane/issues/1170#issuecomment-1169541419, or unsubscribe https://github.com/notifications/unsubscribe-auth/AISPK3M3AR7JJ2MFD6WGKDDVRPLPVANCNFSM52DGUBBA . You are receiving this because you were mentioned.Message ID: @.***>
Description
Hi everyone, I am trying to use openlane and skywater pdk to synthesize my ALU design . When start the flow my config.tcl file i get the following error:
[INFO]: Running Synthesis... [ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /openlane/designs/ALU/runs/RUN_2022.06.28_18.49.22/logs/synthesis/1-synthesis.log |& tee /dev/null" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines:
49.1. Extracting gate netlist of module
\divider_64bit_test' to
/tmp/yosys-abc-NTqtCv/input.blif'.. Extracted 24759 gates and 24888 wires to a netlist network with 129 inputs and 256 outputs.49.1.1. Executing ABC. sh: line 1: 140 Aborted /build/bin/yosys-abc -s -f /tmp/yosys-abc-NTqtCv/abc.script 2>&1 ERROR: ABC: execution of command "/build/bin/yosys-abc -s -f /tmp/yosys-abc-NTqtCv/abc.script 2>&1" failed: return code 134. child process exited abnormally
[INFO]: Generating final set of reports... [INFO]: Created manufacturability report at 'designs/ALU/runs/RUN_2022.06.28_18.49.22/reports/manufacturability.rpt'. [INFO]: Created metrics report at 'designs/ALU/runs/RUN_2022.06.28_18.49.22/reports/metrics.csv'. [INFO]: Saving runtime environment... [ERROR]: Flow failed.
"flow_fail" (procedure "try_catch" line 17) invoked from within "try_catch $::env(SYNTH_BIN) -c $::env(SYNTH_SCRIPT) -l [index_file $::env(synthesis_logs)/synthesis.log] |& tee $::env(TERMINAL_OUTPUT)" (procedure "run_yosys" line 32) invoked from within "run_yosys" (procedure "run_synthesis" line 11) invoked from within "[lindex $step_exe 0] [lindex $step_exe 1] " (procedure "run_non_interactive_mode" line 55) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { if { [info exists arg_values(-file)] } { run_file [file normalize $a..." (file "./flow.tcl" line 434)
Environment
Reproduction Material
cd OpenLane make mount ./flow.tcl -design ALU
Expected behavior
I am expecting some timing slack and violation errors.
Logs