Closed Shrihari01 closed 2 years ago
Have you referred built-in examples? https://github.com/The-OpenROAD-Project/OpenLane/blob/master/designs/APU/config.json
How to run the code in terminal?
Fill issue_template
properly, so i can know which version of OpenLane currently used
This part is incredibly important:
Please run the following shell command in the OpenLane root folder:
python3 ./env.py issue-survey
and paste your log here
WARNING: issue-survey appears to be running inside the OpenLane container.
This makes it difficult to rule out issues with your environment.
Git Log (Last 3 Commits)
Git Remotes
origin https://github.com/The-OpenROAD-Project/OpenLane.git (fetch) origin https://github.com/The-OpenROAD-Project/OpenLane.git (push)
Refer this document https://github.com/The-OpenROAD-Project/OpenLane/blob/master/designs/README.md to create new design.
Place your verilog code insde OpenLane/designs/<design name>/src/
Update config.json
for CLOCK_PORT
and CLOCK_PERIOD
Execute ./flow.tcl -design <design name>
will run yosys and synthesize your verilog code.
How to Update config.json for CLOCK_PORT and CLOCK_PERIOD ?
share your verilog code and top module name.
I will share you config.json
and use the same at your end
// top module name-alu.v
module alu32(in_a,in_b, c_opcode,o_result); input [31:0]in_a,in_b; input [2:0]c_opcode; output [31:0]o_result; reg [31:0]o_result; always@(in_a,in_b,c_opcode) begin case(c_opcode) 3'b000: o_result = in_a + in_b; 3'b001: o_result = in_a - in_b; 3'b010: o_result = in_a + 1; 3'b011: o_result = in_a - 1; 3'b100: o_result = in_a?1:0; // true 3'b101: o_result = ~in_a; // Complement 3'b110: o_result = in_a & in_b; //AND Bitwise 3'b111: o_result = in_a | in_b; // OR Bitwise default : o_result = 32'bx; endcase end endmodule
alu32.zip
Unzip attached file and place alu32
directory under OpenLane/designs/alu32
Run following command, it will complete RTL-GDS2 flow.
cd OpenLane
make mount
./flow.tcl -design alu32
This page specific to report tool related issues. Please read the document and try to understand the flow. Already built-in examples there how to use clock less designs: https://github.com/The-OpenROAD-Project/OpenLane/blob/master/designs/inverter/config.json
Learn from examples and implement your own design. Thanks
How to insert src file and config.json in designs folder of required verilog program ?
To run and test the verilog code