OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
OpenROAD has had an experimental feature to write_liberty for a while. The values reportedly aren't that accurate but we feel like generating a basic lib file for things like synthesis has its merit.
On that note, OpenLane doesn't officially support liberty files for synthesizing designs with macros- requiring black-boxed Verilog models instead.
kareefardi
commented
1 year ago
Prompt
OpenROAD has had an experimental feature to
write_libertyfor a while. The values reportedly aren't that accurate but we feel like generating a basic lib file for things like synthesis has its merit.On that note, OpenLane doesn't officially support liberty files for synthesizing designs with macros- requiring black-boxed Verilog models instead.
Proposal
Add liberty writing (requires #1244 to be merged)