Closed Fraserbc closed 1 year ago
@Fraserbc Is that mean you've synthesized netlist and want to use that file directly by skipping yosys stage right?
@vijayank88 no, I'm running that synthesised netlist through Openlane. I don't want to skip that. But OpenLane only passed when that synthesised netlist is used, if I try and run it on the original verilog, it failed to pass with routing congestion error.
@Fraserbc
Attach routing stage issue_reproducible
generated by flow. We will debug and provide the solution.
Also you're using 3 months old commit. Update OpenLane commit to latest once and try again.
By using simon.v
with latest OpenLane able to complete the flow.
@vijayank88 Sorry, I didn't realise I wasn't using the latest version. TinyTapeout uses caravel_user_project release mpw-7a
which has the outdated version of OpenLane. Thanks for the help.
Description
I have a design that I'm trying to build using OpenLane, but it only passes once I run the design through a yosys synth first.
The design can be found here.
When I run Openlane with
./flow.tcl -verbose 2 -overwrite -design /work/src -run_path /work/runs -tag wokwi
onsimon.v
it failed with routing congestion. But if I instead run this yosys script and OpenLane on the resultingsynth.v
, it passes.To me this makes very little sense, as I can't see what this first yosys pass will do that OpenLane doesn't.
Expected behavior
The design should pass without having to run it through yosys first.
Environment
The actual flow is being run inside the container, but the script instructed me to run it outside.
Reproduction Material
design_notpasses.tar.gz design_passes.tar.gz
It's run with the sky130 PDK in the
efabless/openlane:2022.07.02_01.38.08
docker container.