vijayank88
commented
1 year ago @JiaDYuan
Have you tried to include sram as VERILOG_FILES_BLACKBOX?
Closed JiaDYuan closed 1 year ago
vijayank88
commented
1 year ago @JiaDYuan
Have you tried to include sram as VERILOG_FILES_BLACKBOX?
vijayank88
commented
1 year ago I see only VERILOG_FILES pointing all src/*.v
Not found VERILOG_FILES_BLACKBOX this variable in config.json
JiaDYuan
commented
1 year ago @vijayank88 I include sram now,: { "DESIGN_NAME": "DigitalTop", "VERILOG_FILES": "dir::src/*.v", "CLOCK_PORT": "clk", "CLOCK_PERIOD": 25.0, "DESIGN_IS_CORE": true,
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 2000 3750",
"PL_TARGET_DENSITY": 0.5,
"VDD_NETS": "vccd1",
"GND_NETS": "vssd1",
"MACRO_PLACEMENT_CFG": "dir::macro_placement.cfg",
"EXTRA_LEFS": "/openlane/pdks/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef",
"EXTRA_GDS_FILES": "/openlane/pdks/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds",
"EXTRA_LIBS": "/openlane/pdks/sky130B/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib",
"VERILOG_FILES_BLACKBOX": "dir::bb/*.v",
"RUN_KLAYOUT_XOR": false,
"MAGIC_DRC_USE_GDS": false,
"QUIT_ON_MAGIC_DRC": false}
But I now I get the same error messages as before..........
JiaDYuan
commented
1 year ago 
maliberty
commented
1 year ago Your reproducible doesn't work:
Successfully finished Verilog frontend.
ERROR: Can't open input file `openlane/designs/DigitalTop/src/ClockDividerN.v' for reading: No such file or directory@maliberty
Its bug from issue_reproducible. Created recursive folders for verilog source file names. From DigitalTop.zip you may get required source RTL.
@JiaDYuan Can you share updated config.json will try again at my end?
JiaDYuan
commented
1 year ago @vijayank88 config.json.zip
vijayank88
commented
1 year ago @JiaDYuan
In the DigitalTop.zip I've only src directory.
I'm not found bb/*.v. Can you re-attach the DigitalTop.zip again with updated files?
JiaDYuan
commented
1 year ago DigitalTop.zip @vijayank88
JiaDYuan
commented
1 year ago So it is the problem of syntax error? I tried to synthesize the design in the Vivado, it was synthesized successfully.
vijayank88
commented
1 year ago Even ORFS unable to finish synthesis stage.
10.14. Executing ALUMACC pass (create $alu and $macc cells).
10.15. Executing SHARE pass (SAT-based resource sharing).
Elapsed time: 2:49:35[h:]min:sec. CPU time: user 9786.52 sys 377.98 (99%). Peak memory: 124899820KB.
make: *** [results/sky130hd/DigitalTop/base/1_1_yosys.v] Error 9@JiaDYuan Just for confirmation have you replaced all register into fixed SRAM macro in source RTL?
vijayank88
commented
1 year ago @JiaDYuan Reply got from yosys team
Seems to be running out of memory. Try running synthesis without flattening, and make sure the caches are being mapped to SRAM.Can you try the same?
JiaDYuan
commented
1 year ago @vijayank88
Yes, I have set the synthesis without the Flattening. "SYNTH_NO_FLAT": true.
And now I am checking if all the caches and memories are mapped to SRAM. But it is not easy due to the large scale of BOOM core.
Description
the synthesis process of small BOOM core got killed for unknown reason: child killed: kill signal
Expected Behavior
I want to synthesize the small BOOM core successfully through OpenLane.
Environment report
Reproduction material
DigitalTop.zip
./flow.tcl -design DigitalTop -tag synthesis_only -to synthesis -overwrite
Relevant log output