Open Brajeshp opened 1 year ago
i wish to do a formal verification (logic equalence checks etc) for my designs. i recently came to know about the yosys's sby and eqy tools, but is there any move towards this in openlane's yosys regarding mentioned above?
i have same doubt regarding whether mentioned above is there in flow or not?
thank you.
Request all concerned to clarify, if Formal Verification is part of openlane's RTL-To-GDS automated flow or not.
For details, one can look at starting thread, which is available at following link:-
https://app.slack.com/client/T01699QAZBQ/C016H8WJMBR/thread/C016H8WJMBR-1673179618.744079