Missing function on output ports of `sky130_fd_sc_hd__(s)dlclkp_*`

[kareefardi]

Description

Output ports of such cells have no function and gets rejected by yosys unless the cells are blackboxed.

Expected Behavior

Cells shouldn't be rejected by yosys

Environment report

n/a

Reproduction material

n/a

Relevant log output

sample output:

yosys> read_liberty libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
1. Executing Liberty frontend: libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
ERROR: Missing function on output GCLK of cell sky130_fd_sc_hd__dlclkp_1.

Still investigating a proper fix. Related issue: https://github.com/The-OpenROAD-Project/OpenLane/issues/1627

[tristonw109]

I am currently having the same issue! I also have a similar issue with the nanogate45 tech

[maliberty]

Fwiw I doubt yosys can infer a clock gate.

[tristonw109]

Fwiw I doubt yosys can infer a clock gate.

I need to use the insbuf command in yosy, think I can delete the clock gate section and be ok?

[maliberty]

I need to use the insbuf command in yosy, think I can delete the clock gate section and be ok?

I don't know but it seems odd to use a clock gating cell as a buffer.

[tristonw109]

Fwiw I doubt yosys can infer a clock gate.

Using this comment, I looked into if yosys can infer gated clocks. It doesn't seem to support it. Since I didn't need the gate clock, I removed it from the liberty file and was able to easily load it into yosys. This is a temporary fix until yosys can support gated clocks.