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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
https://openlane.readthedocs.io/
Apache License 2.0
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Provide option to increase pin spacing with pin_order.cfg #1711

Closed vijayank88 closed 1 year ago

vijayank88 commented 1 year ago

Description

Based on comment https://github.com/The-OpenROAD-Project/OpenLane/issues/1699#issuecomment-1488316946 For IO limited block with fixed pin location through pin_order.cfg it is good to add FP_IO_MIN_DISTANCE configuration to keep some minimum distance.

pin_order_issue

in above floorplan, the corner has some more space. As existing pin placement not increasing pin distance. It is good to customize pin distance for better pin placement.

So it will be easy to place buffer and routing, otherwise facing congestion issue.

Proposal

No response

kareefardi commented 1 year ago

@vijayank88 what is the exact configuration to generate what you have in that screenshot?

vijayank88 commented 1 year ago

Increased die size 2600x3010 and ran the OpenLane flow with user design of fixed pin_order.cfg.

kareefardi commented 1 year ago

A bigger issue that I am seeing is not respecting spacing rule. I am trying a fix now however in this design there are 2276 pins. This requires at least a height of 3100 to validly place the pins*. The result would look like this (for the side pins). 2023-04-03_16-26 2023-04-03_16-28

Pin width is 0.6. met3 spacing is 0.3. met3 tracks have a pitch of 0.68. We want to align with met3 tracks and respect met3 spacing so we want to skip a track for each pin. Pins' pitch will be 1.36. Required height would be 1.36 2276

vijayank88 commented 1 year ago

Yes, I agree. Die size should be increased to place all the pins...

hanm2019 commented 1 year ago

make be place in multiple layer? Can I decide the pin's layer also in pin_order.cfg? such as

#LAYER 1
#N 
clk
rst
bypass

#S
xxxx

#LAYER 2
#N 
...
...

#S
...
...
hakan-demirli commented 1 year ago

Yea, multi layer pins would be a good option. Currently only way to control it is via "FPIO{}METAL" option which selects the layer for horizontal or vertical pins. For example,

    "FP_IO_HMETAL": "met1 met3",

The problem is you can not control which pins are on met1 and met3. For two vector adr and data, each 32 bits, it ends up mixed and creates a routing nightmare for the macro.