Open jchin2 opened 1 year ago
kareefardi
commented
1 year ago I think that's due to having no nets in the design. In the log there is Routed nets: 0. I think something should be done at OpenROAD's end to handle no nets when estimating parastics. Regardless, you should disable all optimization steps by disabling the following flags PL_RESIZER_DESIGN_OPTIMIZATIONS, PL_RESIZER_TIMING_OPTIMIZATIONS, GLB_RESIZER_TIMING_OPTIMIZATIONS and GLB_RESIZER_DESIGN_OPTIMIZATIONS
kareefardi
commented
1 year ago Wait something else is wrong. Connection between the pins and the macro is established in the source file. There should be nets in the design. Looking into it ..
kareefardi
commented
1 year ago I think this is happening because the pins in the LEF file of the custom made circuit and the verilog model of the same circuit don't have matching pins. These are the pins found in the LEF
PIN CLK0
PIN CLK1
PIN CLK2
PIN CLK3
PIN Dis0
PIN Dis1
PIN Dis2
PIN Dis3
PIN GND
PIN k0
PIN k0_bar
PIN k1
PIN k1_bar
PIN k2
PIN k2_bar
PIN k3
PIN k3_bar
PIN s0
PIN s0_bar
PIN s1
PIN s1_bar
PIN s2
PIN s2_bar
PIN s3
PIN s3_bar
PIN x0
PIN x0_bar
PIN x1
PIN x1_bar
PIN x2
PIN x2_bar
PIN x3
PIN x3_barWhile these are the pins in the verilog model:
input wire [BIT_SIZE-1:0] clk_in;
input wire [BIT_SIZE-1:0] dis_in;
input wire [BIT_SIZE-1:0] x_in;
input wire [BIT_SIZE-1:0] x_in_bar;
input wire [BIT_SIZE-1:0] k_in;
input wire [BIT_SIZE-1:0] k_in_bar;
output wire [BIT_SIZE-1:0] s_out;
output wire [BIT_SIZE-1:0] s_out_bar;
jchin2
commented
1 year ago I will try it out and make a report of the results.
jchin2
commented
1 year ago I've reassigned the pins and increased the die area to get pass [Error GRT-0076] Net net1 not properly covered. Currently I'm having lvs error about VPWR and VGND pins? I have also tried disabling LVS_INSERT_POWER_PINS, but my lvs result is a mismatch in a netlist mismatch. I have two config files with LVS_INSERT_POWER_PINS on and off. 40-write_powered_def.log is associated with LVS_INSERT_POWER_PINS on. 40-lvs.lef.log is associated with LVS_INSERT_POWER_PINS off. I also included the verilog files that have been changed within the top_wrapper_and_blackbox_verilog.zip folder 40-write_powered_def.log config_LVS_INSERT_POWER_PINS_off.zip config_LVS_INSERT_POWER_PINS_on.zip 40-lvs.lef.log top_wrapper_and_blackbox_verilog.zip
jchin2
commented
1 year ago I made a mistake in closing it...
kareefardi
commented
1 year ago Looks like the macro is not connected to power/gnd. Somehow, magic and netgen are flagging this missing connection. I am still investigating.
kareefardi
commented
1 year ago Looks like this is the issue https://github.com/RTimothyEdwards/magic/issues/260#issuecomment-1657118652. It is a design issue. The tools are functioning correctly.
jchin2
commented
1 year ago Thank you for looking into the issue. It is good to know the tools are functioning as intended and I will explore the link you have provided. My question is do I have to make the pin names in the lef/gds to be verilog friendly format?
Since the verilog model for the blackbox is something like this:
input wire [BIT_SIZE-1:0] k_in; input wire [BIT_SIZE-1:0] k_in_bar; output wire [BIT_SIZE-1:0] s_out; output wire [BIT_SIZE-1:0] s_out_bar;
would you recommend use of the following format:"s_out[0], s_out_bar[0], ... , s_out[31], s_out_bar[31]" for the layout pin names to make it easier for OpenLane to connect them? My motivation for wanting to do this is to accommodate for a much larger custom circuit down the line.
kareefardi
commented
1 year ago The format doesn't matter that much. It is just that they need to match each other. Whatever you chose be careful of escaping.
jchin2
commented
1 year ago Hi @kareefardi , I've updated the blackbox model and gds to have the verilog bus notation format. I've found out openlane seems to preserve the dimension and scale of blackbox gds generated from magic. Currently I'm facing an issue in "Generating PDN" phase where it is complaining about No regex match found. I've uploaded some of the file related to the issue. current_state.zip The VDD for my current case is acting as a dummy to trick openlane to fulfill the power connections. The blackbox circuit uses trapezoidal wave to power the circuit and we are thinking of providing the power externally. The GND for this is the same where we want it to be connected to a GPIO pin. How would we go about doing that?
Description
Hi, I'm attempting to make test blackbox out of a custom circuit and ran into
[ERROR RSZ-0005] Run global_route before estimating parasitics for global routing.I tried playing with the routing commands in config.json, however I'm lacking understanding to what the error log wants me to fix. I've turnedGRT_ESTIMATE_PARASITICSon and off to no great effect. The -interactive console is currently not available to me as the moment of writing due to a tool bug.Expected Behavior
A generation of a blackbox with a "top wrapper circuit" around it.
Environment report
Reproduction material
issue_reproducible.zip bb.zip building_blocks.zip src.zip I have included the config.json file within src.zip as well.
Relevant log output