The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
https://openlane.readthedocs.io/
Apache License 2.0
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addition of block of lines in synth.tcl is not reflecting in synthesis.log #1955

Closed Vinayakamk closed 1 year ago

Vinayakamk commented 1 year ago

Description

hello i just want to add a SYNTH_RETIME as a config varible,or any if statemnt in synth.tcl of openlane,which ask user whether to do retime or not,so that i can do retiming just by passing true for the SYnTH_RETIME in config.json.i am imitating SYNTH_AUTONAME. image

but synth retime is not reflecting in sythesis.log where in synth autoname happened. though the commands are valid in yosys

Proposal

the synth.tcl or the flow.tcl should allow the user defined tcl commands to execute normally(as in this case its not happening). or atleast it should call and excute userdefined .tcl where ever we want during synthesis

vijayank88 commented 1 year ago

@Vinayakamk Share your tcl script and config.json. Try with spm design or share a design which you're trying to implement.

Vinayakamk commented 1 year ago

hello sir,im trying with openlanes picorv32 either i want retiming should happen in synthesis stage like other config.json variable happen. synth.txt //added retime if statement in line no 348 config.txt //added true value for the synth_retime

if it is not possible,flow.tcl should take my tcl files which does retiming,on true value set in config.json.

user_env.txt automatc.txt retime.txt

(i have sent my 3 tcl files in .txt) i want to incorporate the retiming concept it flow.tcl in any of the above way

donn commented 1 year ago

Please re-file this as an issue. We'll need a lot more information to figure out why this is happening as technically, modifying a script should modify the execution.

Vinayakamk commented 1 year ago

sure thanks for the reply,,,