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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
https://openlane.readthedocs.io/
Apache License 2.0
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Using Openlane for symmetric routing #2031

Open jchin2 opened 8 months ago

jchin2 commented 8 months ago

Hi all, I am laying out a circuit for security based application and they are dependent on balanced parasitic capacitance in its routing. The criteria is all the routing from within the custom standard cells, inter cell connections, to macro-macro routing has to be symmetrical. Motivation is to get balanced parasitic capacitance between them. This circuit uses 4 trapezoidal power clocks at 90 degree phase shift and the sequence follows CLK0 to CLK3. The following images below show the current layout outline, 4-bit width layout, and new layout outline plan for symmetric routing. I recognize I will need to reroute the basic custom cells to realize the new plan, just to make sure they are matched on the lowest hierarchy. The question is does Openlane have some sort of function to facilitate balanced inter-cell or inter-macro routing? Current 4-bit width layout outline. image 4-bit width Layout sub-block without considering its parasitic capacitance balance. image New logic cell placement plan in vertical pipeline image

jchin2 commented 8 months ago

@kareefardi Please kindly find the design files in the attachment. Design_files_11012023.zip