OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Adds support for VERILOG_INCLUDE_DIRS option to Verilator linter (in synthesis.tcl command run_verilator)
This option is already supported in synthesis by yosys, so it would be nice if it would also work with linter. Without it, some designs that are synthesized fine, cannot pass the linter.
If preferred, this option could be renamed to LINTER_INCLUDE_DIRS, as a independent option from yosys one. I'm not sure which one would fit better.
Adds support for
VERILOG_INCLUDE_DIRSoption to Verilator linter (insynthesis.tclcommandrun_verilator)This option is already supported in synthesis by yosys, so it would be nice if it would also work with linter. Without it, some designs that are synthesized fine, cannot pass the linter.
If preferred, this option could be renamed to
LINTER_INCLUDE_DIRS, as a independent option from yosys one. I'm not sure which one would fit better.