Segmentation violation at placement resizer design optimizations

[yunuseryilmaz18]

Description

Hello, I'm using the gfmpw-1b tagged version of the caravel-user-project to harden my macro. I got these crash errors in the Placement Resizer Design Optimizations step:

[STEP 12]
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/yunus/caravel_user_project/openlane/fpga_core_v2/runs/23_11_30_12_02/logs/placement/12-resizer.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer.tcl
[ERROR]: Log: ../home/yunus/caravel_user_project/openlane/fpga_core_v2/runs/23_11_30_12_02/logs/placement/12-resizer.log
[ERROR]: Last 10 lines:
41# 0x00007F01CD268F1E in /lib64/libtcl8.5.so
42# Tcl_EvalEx in /lib64/libtcl8.5.so
43# Tcl_Eval in /lib64/libtcl8.5.so
44# sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*) in openroad
45# ord::tclAppInit(Tcl_Interp*) in openroad
46# Tcl_Main in /lib64/libtcl8.5.so
47# main in openroad
48# __libc_start_main in /lib64/libc.so.6
49# 0x0000000000D3DC77 in openroad
child killed: segmentation violation

Expected Behavior

I was expecting to finish the flow without errors.

Environment report

Kernel: Linux v6.2.0-37-generic
Distribution: ubuntu 22.04
Python: v3.10.12 (OK)
Container Engine: docker v24.0.7 (OK)
OpenLane Git Version: 7ea7a2aeef4bea5445d133c26ca2b3e9f0d0c78f
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: FAILED
/home/yunus/caravel_user_project/dependencies/openlane_src/pdks/sky130A not found.
Traceback (most recent call last):
  File "/home/yunus/caravel_user_project/dependencies/openlane_src/dependencies/verify_versions.py", line 75, in verify_versions
    raise Exception(f"{pdk_dir} not found.")
Exception: /home/yunus/caravel_user_project/dependencies/openlane_src/pdks/sky130A not found.

Failed to verify sky130A.
---
Git Log (Last 3 Commits)

7ea7a2a 2023-10-15T17:01:59+03:00 Fix `FP_PIN_ORDER_CFG` being overriden (#2017) - Kareem Farid -  (grafted, HEAD, tag: 2023.10.16)
---
Git Remotes

origin  https://github.com/The-OpenROAD-Project/OpenLane (fetch)
origin  https://github.com/The-OpenROAD-Project/OpenLane (push)

Reproduction material

issue_reproducible.zip

Relevant log output

[STEP 12]
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/yunus/caravel_user_project/openlane/fpga_core_v2/runs/23_11_30_12_02/logs/placement/12-resizer.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer.tcl
[ERROR]: Log: ../home/yunus/caravel_user_project/openlane/fpga_core_v2/runs/23_11_30_12_02/logs/placement/12-resizer.log
[ERROR]: Last 10 lines:
41# 0x00007F01CD268F1E in /lib64/libtcl8.5.so
42# Tcl_EvalEx in /lib64/libtcl8.5.so
43# Tcl_Eval in /lib64/libtcl8.5.so
44# sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*) in openroad
45# ord::tclAppInit(Tcl_Interp*) in openroad
46# Tcl_Main in /lib64/libtcl8.5.so
47# main in openroad
48# __libc_start_main in /lib64/libc.so.6
49# 0x0000000000D3DC77 in openroad
child killed: segmentation violation

[d-m-bailey]

It's looking for /home/yunus/caravel_user_project/dependencies/openlane_src/pdks/sky130A when it should be looking for gf180mcuD.

Do you have any environment variables set?

env | grep PDK
env | grep TAG
env | grep COMMIT

[yunuseryilmaz18]

No, I didn't set them because they don't mention setting TAG and COMMIT variables. After seeing your comment, I set the PDK variable but the result didn't change.

[d-m-bailey]

Setting the variables can cause problems. I wanted you to check that they were not set.

[d-m-bailey]

We're on gfmpw-1c now. Check that make setup runs without errors.

[yunuseryilmaz18]

I've switched to gfmpw-1c, set PDK variable and run make-setup without errors. I run user_proj_example without errors but I still get the same error with my project.

Issue reproducible file: issue_reproducible.zip

[kareefardi]

I can confirm the issue using latest OpenROAD.

[maliberty]

I started to take a look. I'm wondering why I see:

read_liberty -corner Typical pdk/gf180mcuD/libs.ref/gf180mcu_fd_sc_mcu9t5v0/liberty/gf180mcu_fd_sc_mcu9t5v0__tt_025C_5v00.lib
read_liberty -corner Typical pdk/gf180mcuD/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib

it appears you are loading both 9t & 7t libraries which seems odd. Is there a reason for that?

[maliberty]

If I remove the 7t lib the crash is gone. I think you are loading it only for one corner which is triggering the issue. I'll put an error message in but I think the solution is just to drop the unneeded library.

[yunuseryilmaz18]

@maliberty I'm using 9t cells for the design and if don't add a configuration variable about library, the flow gives an error about it can't find definition of the cell. What should I do to only call 9t cells? Does removing mean deleting from the system?

[maliberty]

@kareefardi would you explain how to do it in OL as I'm not an expert.

[kareefardi]

It might be a flow error. Let me check what's happening.

[kareefardi]

@yunuseryilmaz18 can you share your design input configuration ?

[kareefardi]

@yunuseryilmaz18 I think if you also set STD_CELL_LIBRARY_OPT to 9t the flow should avoid loading the 7t lib and avoid the crash above

[yunuseryilmaz18]

Yes, it did solve. Thank you!

The confusing part for me is STD_CELL_LIBRARY_OPT variable is STD_CELL_LIBRARY in default. However, in my situation it wasn't. I was defining only STD_CELL_LIBRARY.

The config file I used:

{
      "DESIGN_NAME": "grid_clb",
      "DESIGN_IS_CORE": 0,
      "VERILOG_FILES": "dir::rtl/fabric_netlists.v",
      "CLOCK_PERIOD": 300,
      "CLOCK_PORT": "top_width_0_height_0_subtile_0__pin_clk_0_",
      "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu9t5v0",
      "RUN_LINTER": 0,
      "SYNTH_READ_BLACKBOX_LIB": 1
}

[maliberty]

@kareefardi I think the defaults should be updated to only 9t

[kareefardi]

@yunuseryilmaz18 @maliberty I agree that this is confusing and shouldn't happen. I will work on a fix.