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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
https://openlane.readthedocs.io/
Apache License 2.0
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Ameliorate Warnings, PDN Generation, and the default design #2066

Closed donn closed 6 months ago

donn commented 6 months ago

~ Reimplemented the default serial/parallel multiplier to be a bit less cryptic and eliminate linter warnings; and added a proper testbench ~ Reimplemented deprecated variable translation behavior to account for the situation where a deprecated variable's value does not match the default for the new value, which causes a crash ~ Slightly improved warning for designs having been black-boxed during STA ~ PDN Generation Updates ~ Renamed DESIGN_IS_CORE to FP_PDN_MULTILAYER with translation behavior ~ PDN generation will now always attempt to extend to core ring (which is inert if core rings do not exist) ~ Fixed bug where FP_PDN_MULTILAYER being set to 0 would attempt to create a core-ring on two layers anyway ~ IR drop now prints a warning if VSRC_LOC_FILE is not provided

Depends on https://github.com/efabless/openlane-ci-designs/pull/5

kareefardi commented 6 months ago

Can you also do same as https://github.com/efabless/openlane2-ci-designs/pull/14 here. Should fix https://github.com/The-OpenROAD-Project/OpenLane/issues/1978