Closed mbaykenar closed 5 months ago
Uploaded src and config files
After I changed power connections from 8 pins to 2 pins, where only digital powers are connected, the error has gone.
in top Verilog file:
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
in config.tcl file:
set ::env(VDD_NETS) "vccd1" set ::env(GND_NETS) "vssd1"
I am closing this issue since now I can harden macros.
Description
The flow crashes whenever I tried a macro hardening with the parameters:
set ::env(FP_PDN_CORE_RING) 0 set ::env(FP_PDN_MULTILAYER) 0
The fail happens in "Streaming out GDSII with KLayout" step.
If I set these parameters flow completes successfully.
Expected Behavior
A clear macro hardening flow is expected
Environment report
Reproduction material
31-gdsii.log 31-lef.log
Relevant log output