flow succeeds even if clock signal wire is unconnected / doesn't exist

[mattvenn]

Description

Providing a nonexistent clock (should be wb_clk) in user_project_wrapper:

wb_buttons_leds wb_buttons_leds (                                                                                                                                                                         
      .wb_clk_i(wb_clk),                                                                                                                                                                                    
      .wb_rst_i(wb_rst_i),                  

The flow finishes with no errors and the wb_clk_i pin is unconnected.

Expected Behavior

Flow should fail if a net is nonexistent. Flow should fail STA if user clock is missing

Environment report

Kernel: Linux v5.15.0-91-generic
Distribution: ubuntu 20.04
Python: v3.8.10 (OK)
Container Engine: docker v20.10.21 (OK)
OpenLane Git Version: d054702b2cce04761cc2bc598f6b95c9d8ca7c6c
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: OK
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Git Log (Last 3 Commits)

d054702 2023-07-19T16:09:15+03:00 remove `unset_propagated_clock` (#1908) - passant5 -  (grafted, HEAD, tag: 2023.07.19)
---
Git Remotes

origin  https://github.com/The-OpenROAD-Project/OpenLane (fetch)
origin  https://github.com/The-OpenROAD-Project/OpenLane (push)

Reproduction material

to rebuild you need this repo cloned in verilog/rtl/ https://github.com/mattvenn/wishbone_buttons_leds caravel_user_project : https://github.com/mattvenn/caravel_user_project_mpw9e/tree/interview_working

Relevant log output

INFO]: Saving runtime environment...                                                                                                                                                                         
[INFO]: Generating final set of reports...                                                             
[INFO]: Created manufacturability report at '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_15_13/reports/manufacturability.rpt'.              
[INFO]: Created metrics report at '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_15_13/reports/metrics.csv'.                                  
[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_1
5_13/reports/signoff/21-rcx_sta.checks.rpt'.                                                                                                                                                                  
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10
_15_13/reports/signoff/21-rcx_sta.checks.rpt'.                                                         
[INFO]: There are no hold violations in the design at the typical corner.                                                                                                                                     
[INFO]: There are no setup violations in the design at the typical corner.                             
[SUCCESS]: Flow complete.                                                                                                                                                                                     
[INFO]: Note that the following warnings have been generated:                                          
[WARNING]: Module sky130_fd_sc_hd__fill_2 blackboxed during sta                                        
[WARNING]: Module sky130_fd_sc_hd__fill_1 blackboxed during sta                                        
[WARNING]: Module sky130_ef_sc_hd__decap_12 blackboxed during sta                                      
[WARNING]: Module sky130_fd_sc_hd__tapvpwrvgnd_1 blackboxed during sta                                 
[WARNING]: VSRC_LOC_FILES is not defined. The IR drop analysis will run, but the values may be inaccurate.                                                                                                    
[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10_1
5_13/reports/signoff/21-rcx_sta.checks.rpt'.                                                                                                                                                                  
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane/user_project_wrapper/runs/24_01_10
_15_13/reports/signoff/21-rcx_sta.checks.rpt'.                                                                                                                                                                

make[1]: Leaving directory '/home/matt/work/asic-workshop/shuttle-mpw9/caravel_user_project/openlane'

[kareefardi]

The linter is disabled in your configuration. I am not sure why yosys didn't catch this though yet.

[kareefardi]

@mattvenn Also I believe yosys passed because of this https://github.com/mattvenn/caravel_user_project_mpw9e/blob/a2d1a4b8a3d980b9a5e843b9922fc98e9ef70ba7/verilog/rtl/user_project_wrapper.v#L104C1-L105C22 - Making it accept implicitly declared wires. Probably related to this issue in yosys https://github.com/YosysHQ/yosys/issues/1217

[mattvenn]

I just copied the default config from the user project example. So if the linter is off, then it should be turned on in the example.

Thanks for linking the bug in yosys, that's a serious issue IMO.

[kareefardi]

@mattvenn Perhaps you could open an issue in the example repo.