OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Hello all, I'm having issues using the SYNTH_PARAMETERS option.
My Verilog design consists of a number of parametric modules. The top-level module has parameters as well, which get forwarded to the proper sub-modules. Some of the parameters are used in a generate statement.
The top-level module has 4 parameters with defaults:
According to this the following SYNTH_PARAMETERS syntax is correct:
// From my config.tcl
set ::env(SYNTH_PARAMETERS) "NUM_INPUTS=1 NUM_OUTPUTS=1 WIDTH=8 FRAC_BITS=5"
However, the synthesis keeps complaining about ports having no drivers, then trims them and I eventually get an empty design, and the tool exits with an error. Please note that I have already checked all wires, ports, etc and everything is properly connected. So those warnings are wrong. Proof of this is that when I remove the above SYNTH_PARAMETERS option and change the defaults at the top-level to match those from the SYNTH_PARAMETERS option, everything goes as expected and synthesis finishes successfully.
It seems to me there are problems with the hierarchy when submodules too have parameters. I modified the synthesis script under scripts/yosys and appended the hierarchy command here and there, but with no luck.
Any idea?
Here's the output of python3 ./env.py issue-survey
Hello all, I'm having issues using the
SYNTH_PARAMETERS
option.My Verilog design consists of a number of parametric modules. The top-level module has parameters as well, which get forwarded to the proper sub-modules. Some of the parameters are used in a
generate
statement.The top-level module has 4 parameters with defaults:
According to this the following
SYNTH_PARAMETERS
syntax is correct:However, the synthesis keeps complaining about ports having no drivers, then trims them and I eventually get an empty design, and the tool exits with an error. Please note that I have already checked all wires, ports, etc and everything is properly connected. So those warnings are wrong. Proof of this is that when I remove the above
SYNTH_PARAMETERS
option and change the defaults at the top-level to match those from theSYNTH_PARAMETERS
option, everything goes as expected and synthesis finishes successfully.It seems to me there are problems with the hierarchy when submodules too have parameters. I modified the synthesis script under
scripts/yosys
and appended thehierarchy
command here and there, but with no luck.Any idea?
Here's the output of
python3 ./env.py issue-survey
Many thanks S