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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
https://openlane.readthedocs.io/
Apache License 2.0
1.31k stars 368 forks source link

OpenLane deleting modules while synthesizing #2092

Closed Ashutosh-3107 closed 7 months ago

Ashutosh-3107 commented 7 months ago

Description

During flattening OpenLane deletes the modules and is unable to synthesisze and map it to standard library

Expected Behavior

Not expecting to delete the modules while flattening

Environment report

open_pdks cd1748bb197f9b7af62a54507de6624e30363943
Kernel: Linux v5.15.133.1-microsoft-standard-WSL2
Distribution: ubuntu 22.04
Python: v3.10.12 (OK)
Container Engine: docker v24.0.5 (OK)
OpenLane Git Version: 9dbd8b5ea2bd891bed4dcc97df5c7439083f0368
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

9dbd8b5 2024-01-11T15:26:56+02:00 Fix `-synth_explore` crash (#2085) - Kareem Farid -  (grafted, HEAD -> master, tag: 2024.01.12, origin/master, origin/HEAD)
---
Git Remotes

origin  https://github.com/The-OpenROAD-Project/OpenLane.git (fetch)
origin  https://github.com/The-OpenROAD-Project/OpenLane.git (push)

Reproduction material

https://github.com/merldsu/RISCV_Pipeline_Core

Relevant log output

/----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.34 (git sha1 4a1b5599258, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Hazard_unit.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Hazard_unit.v' to AST representation.
Generating RTLIL representation for module `\hazard_unit'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Data_Memory.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Data_Memory.v' to AST representation.
Generating RTLIL representation for module `\Data_Memory'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/ALU.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/ALU.v' to AST representation.
Generating RTLIL representation for module `\ALU'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Sign_Extend.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Sign_Extend.v' to AST representation.
Generating RTLIL representation for module `\Sign_Extend'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Register_File.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Register_File.v' to AST representation.
Generating RTLIL representation for module `\Register_File'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/ALU_Decoder.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/ALU_Decoder.v' to AST representation.
Generating RTLIL representation for module `\ALU_Decoder'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Main_Decoder.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Main_Decoder.v' to AST representation.
Generating RTLIL representation for module `\Main_Decoder'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Control_Unit_Top.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Control_Unit_Top.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit_Top'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Instruction_Memory.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Instruction_Memory.v' to AST representation.
Generating RTLIL representation for module `\Instruction_Memory'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Mux.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Mux.v' to AST representation.
Generating RTLIL representation for module `\Mux'.
Generating RTLIL representation for module `\Mux_3_by_1'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/PC_Adder.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/PC_Adder.v' to AST representation.
Generating RTLIL representation for module `\PC_Adder'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/PC.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/PC.v' to AST representation.
Generating RTLIL representation for module `\PC_Module'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Writeback_Cycle.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Writeback_Cycle.v' to AST representation.
Generating RTLIL representation for module `\writeback_cycle'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Memory_Cycle.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Memory_Cycle.v' to AST representation.
Generating RTLIL representation for module `\memory_cycle'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Execute_Cycle.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Execute_Cycle.v' to AST representation.
Generating RTLIL representation for module `\execute_cycle'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Decode_Cyle.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Decode_Cyle.v' to AST representation.
Generating RTLIL representation for module `\decode_cycle'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Fetch_Cycle.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Fetch_Cycle.v' to AST representation.
Generating RTLIL representation for module `\fetch_cycle'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: /openlane/designs/Pipeline_top/src/Pipeline_top.v
Parsing SystemVerilog input from `/openlane/designs/Pipeline_top/src/Pipeline_top.v' to AST representation.
Generating RTLIL representation for module `\Pipeline_top'.
Successfully finished Verilog frontend.

19. Generating Graphviz representation of design.
Writing dot description to `/openlane/designs/Pipeline_top/runs/run1/tmp/synthesis/hierarchy.dot'.
Dumping module Pipeline_top to page 1.

20. Executing HIERARCHY pass (managing design hierarchy).

20.1. Analyzing design hierarchy..
Top module:  \Pipeline_top
Used module:     \hazard_unit
Used module:     \writeback_cycle
Used module:         \Mux
Used module:     \memory_cycle
Used module:         \Data_Memory
Used module:     \execute_cycle
Used module:         \PC_Adder
Used module:         \ALU
Used module:         \Mux_3_by_1
Used module:     \decode_cycle
Used module:         \Sign_Extend
Used module:         \Register_File
Used module:         \Control_Unit_Top
Used module:             \ALU_Decoder
Used module:             \Main_Decoder
Used module:     \fetch_cycle
Used module:         \Instruction_Memory
Used module:         \PC_Module

20.2. Analyzing design hierarchy..
Top module:  \Pipeline_top
Used module:     \hazard_unit
Used module:     \writeback_cycle
Used module:         \Mux
Used module:     \memory_cycle
Used module:         \Data_Memory
Used module:     \execute_cycle
Used module:         \PC_Adder
Used module:         \ALU
Used module:         \Mux_3_by_1
Used module:     \decode_cycle
Used module:         \Sign_Extend
Used module:         \Register_File
Used module:         \Control_Unit_Top
Used module:             \ALU_Decoder
Used module:             \Main_Decoder
Used module:     \fetch_cycle
Used module:         \Instruction_Memory
Used module:         \PC_Module
Removed 0 unused modules.
Renaming module Pipeline_top to Pipeline_top.

21. Executing TRIBUF pass.

22. Executing HIERARCHY pass (managing design hierarchy).

22.1. Analyzing design hierarchy..
Top module:  \Pipeline_top
Used module:     \hazard_unit
Used module:     \writeback_cycle
Used module:         \Mux
Used module:     \memory_cycle
Used module:         \Data_Memory
Used module:     \execute_cycle
Used module:         \PC_Adder
Used module:         \ALU
Used module:         \Mux_3_by_1
Used module:     \decode_cycle
Used module:         \Sign_Extend
Used module:         \Register_File
Used module:         \Control_Unit_Top
Used module:             \ALU_Decoder
Used module:             \Main_Decoder
Used module:     \fetch_cycle
Used module:         \Instruction_Memory
Used module:         \PC_Module

22.2. Analyzing design hierarchy..
Top module:  \Pipeline_top
Used module:     \hazard_unit
Used module:     \writeback_cycle
Used module:         \Mux
Used module:     \memory_cycle
Used module:         \Data_Memory
Used module:     \execute_cycle
Used module:         \PC_Adder
Used module:         \ALU
Used module:         \Mux_3_by_1
Used module:     \decode_cycle
Used module:         \Sign_Extend
Used module:         \Register_File
Used module:         \Control_Unit_Top
Used module:             \ALU_Decoder
Used module:             \Main_Decoder
Used module:     \fetch_cycle
Used module:         \Instruction_Memory
Used module:         \PC_Module
Removed 0 unused modules.

23. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

24. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/openlane/designs/Pipeline_top/src/Fetch_Cycle.v:64$196 in module fetch_cycle.
Marked 1 switch rules as full_case in process $proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194 in module decode_cycle.
Marked 1 switch rules as full_case in process $proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191 in module execute_cycle.
Marked 1 switch rules as full_case in process $proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189 in module memory_cycle.
Marked 1 switch rules as full_case in process $proc$/openlane/designs/Pipeline_top/src/PC.v:21$187 in module PC_Module.
Marked 1 switch rules as full_case in process $proc$/openlane/designs/Pipeline_top/src/Register_File.v:24$81 in module Register_File.
Marked 1 switch rules as full_case in process $proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:23$31 in module Data_Memory.
Removed a total of 0 dead cases.

25. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 31 redundant assignments.
Promoted 15 assignments to connections.

26. Executing PROC_INIT pass (extract init attributes).

27. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \rst in `\fetch_cycle.$proc$/openlane/designs/Pipeline_top/src/Fetch_Cycle.v:64$196'.
Found async reset \rst in `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
Found async reset \rst in `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
Found async reset \rst in `\memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.

28. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~3 debug messages>

29. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\fetch_cycle.$proc$/openlane/designs/Pipeline_top/src/Fetch_Cycle.v:64$196'.
     1/3: $0\PCPlus4F_reg[31:0]
     2/3: $0\PCF_reg[31:0]
     3/3: $0\InstrF_reg[31:0]
Creating decoders for process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
     1/14: $0\RS2_D_r[4:0]
     2/14: $0\RS1_D_r[4:0]
     3/14: $0\PCPlus4D_r[31:0]
     4/14: $0\PCD_r[31:0]
     5/14: $0\RD_D_r[4:0]
     6/14: $0\Imm_Ext_D_r[31:0]
     7/14: $0\RD2_D_r[31:0]
     8/14: $0\RD1_D_r[31:0]
     9/14: $0\ALUControlD_r[2:0]
    10/14: $0\BranchD_r[0:0]
    11/14: $0\ResultSrcD_r[0:0]
    12/14: $0\MemWriteD_r[0:0]
    13/14: $0\ALUSrcD_r[0:0]
    14/14: $0\RegWriteD_r[0:0]
Creating decoders for process `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
     1/7: $0\ResultE_r[31:0]
     2/7: $0\RD2_E_r[31:0]
     3/7: $0\PCPlus4E_r[31:0]
     4/7: $0\RD_E_r[4:0]
     5/7: $0\ResultSrcE_r[0:0]
     6/7: $0\MemWriteE_r[0:0]
     7/7: $0\RegWriteE_r[0:0]
Creating decoders for process `\memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.
     1/6: $0\ReadDataM_r[31:0]
     2/6: $0\ALU_ResultM_r[31:0]
     3/6: $0\PCPlus4M_r[31:0]
     4/6: $0\RD_M_r[4:0]
     5/6: $0\ResultSrcM_r[0:0]
     6/6: $0\RegWriteM_r[0:0]
Creating decoders for process `\PC_Module.$proc$/openlane/designs/Pipeline_top/src/PC.v:21$187'.
     1/1: $0\PC[31:0]
Creating decoders for process `\Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
Creating decoders for process `\Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:0$97'.
Creating decoders for process `\Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:24$81'.
     1/3: $1$memwr$\Register$/openlane/designs/Pipeline_top/src/Register_File.v:27$79_EN[31:0]$89
     2/3: $1$memwr$\Register$/openlane/designs/Pipeline_top/src/Register_File.v:27$79_DATA[31:0]$88
     3/3: $1$memwr$\Register$/openlane/designs/Pipeline_top/src/Register_File.v:27$79_ADDR[4:0]$87
Creating decoders for process `\Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:0$42'.
Creating decoders for process `\Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:23$31'.
     1/3: $1$memwr$\mem$/openlane/designs/Pipeline_top/src/Data_Memory.v:26$29_EN[31:0]$37
     2/3: $1$memwr$\mem$/openlane/designs/Pipeline_top/src/Data_Memory.v:26$29_DATA[31:0]$36
     3/3: $1$memwr$\mem$/openlane/designs/Pipeline_top/src/Data_Memory.v:26$29_ADDR[31:0]$35

30. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\Instruction_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:26$153_EN' from process `\Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
No latch inferred for signal `\Instruction_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:27$154_EN' from process `\Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
No latch inferred for signal `\Instruction_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:28$155_EN' from process `\Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
No latch inferred for signal `\Instruction_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:29$156_EN' from process `\Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
No latch inferred for signal `\Instruction_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:30$157_EN' from process `\Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
No latch inferred for signal `\Instruction_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:31$158_EN' from process `\Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
No latch inferred for signal `\Instruction_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:32$159_EN' from process `\Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
No latch inferred for signal `\Register_File.$memwr$\Register$/openlane/designs/Pipeline_top/src/Register_File.v:34$80_EN' from process `\Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:0$97'.
No latch inferred for signal `\Data_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Data_Memory.v:32$30_EN' from process `\Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:0$42'.

31. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\fetch_cycle.\InstrF_reg' using process `\fetch_cycle.$proc$/openlane/designs/Pipeline_top/src/Fetch_Cycle.v:64$196'.
  created $adff cell `$procdff$225' with positive edge clock and negative level reset.
Creating register for signal `\fetch_cycle.\PCF_reg' using process `\fetch_cycle.$proc$/openlane/designs/Pipeline_top/src/Fetch_Cycle.v:64$196'.
  created $adff cell `$procdff$226' with positive edge clock and negative level reset.
Creating register for signal `\fetch_cycle.\PCPlus4F_reg' using process `\fetch_cycle.$proc$/openlane/designs/Pipeline_top/src/Fetch_Cycle.v:64$196'.
  created $adff cell `$procdff$227' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\RegWriteD_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$228' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\ALUSrcD_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$229' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\MemWriteD_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$230' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\ResultSrcD_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$231' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\BranchD_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$232' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\ALUControlD_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$233' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\RD1_D_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$234' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\RD2_D_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$235' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\Imm_Ext_D_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$236' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\RD_D_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$237' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\RS1_D_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$238' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\RS2_D_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$239' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\PCD_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$240' with positive edge clock and negative level reset.
Creating register for signal `\decode_cycle.\PCPlus4D_r' using process `\decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
  created $adff cell `$procdff$241' with positive edge clock and negative level reset.
Creating register for signal `\execute_cycle.\RegWriteE_r' using process `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
  created $adff cell `$procdff$242' with positive edge clock and negative level reset.
Creating register for signal `\execute_cycle.\MemWriteE_r' using process `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
  created $adff cell `$procdff$243' with positive edge clock and negative level reset.
Creating register for signal `\execute_cycle.\ResultSrcE_r' using process `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
  created $adff cell `$procdff$244' with positive edge clock and negative level reset.
Creating register for signal `\execute_cycle.\RD_E_r' using process `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
  created $adff cell `$procdff$245' with positive edge clock and negative level reset.
Creating register for signal `\execute_cycle.\PCPlus4E_r' using process `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
  created $adff cell `$procdff$246' with positive edge clock and negative level reset.
Creating register for signal `\execute_cycle.\RD2_E_r' using process `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
  created $adff cell `$procdff$247' with positive edge clock and negative level reset.
Creating register for signal `\execute_cycle.\ResultE_r' using process `\execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
  created $adff cell `$procdff$248' with positive edge clock and negative level reset.
Creating register for signal `\memory_cycle.\RegWriteM_r' using process `\memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.
  created $adff cell `$procdff$249' with positive edge clock and negative level reset.
Creating register for signal `\memory_cycle.\ResultSrcM_r' using process `\memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.
  created $adff cell `$procdff$250' with positive edge clock and negative level reset.
Creating register for signal `\memory_cycle.\RD_M_r' using process `\memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.
  created $adff cell `$procdff$251' with positive edge clock and negative level reset.
Creating register for signal `\memory_cycle.\PCPlus4M_r' using process `\memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.
  created $adff cell `$procdff$252' with positive edge clock and negative level reset.
Creating register for signal `\memory_cycle.\ALU_ResultM_r' using process `\memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.
  created $adff cell `$procdff$253' with positive edge clock and negative level reset.
Creating register for signal `\memory_cycle.\ReadDataM_r' using process `\memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.
  created $adff cell `$procdff$254' with positive edge clock and negative level reset.
Creating register for signal `\PC_Module.\PC' using process `\PC_Module.$proc$/openlane/designs/Pipeline_top/src/PC.v:21$187'.
  created $dff cell `$procdff$255' with positive edge clock.
Creating register for signal `\Register_File.$memwr$\Register$/openlane/designs/Pipeline_top/src/Register_File.v:27$79_ADDR' using process `\Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:24$81'.
  created $dff cell `$procdff$256' with positive edge clock.
Creating register for signal `\Register_File.$memwr$\Register$/openlane/designs/Pipeline_top/src/Register_File.v:27$79_DATA' using process `\Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:24$81'.
  created $dff cell `$procdff$257' with positive edge clock.
Creating register for signal `\Register_File.$memwr$\Register$/openlane/designs/Pipeline_top/src/Register_File.v:27$79_EN' using process `\Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:24$81'.
  created $dff cell `$procdff$258' with positive edge clock.
Creating register for signal `\Data_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Data_Memory.v:26$29_ADDR' using process `\Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:23$31'.
  created $dff cell `$procdff$259' with positive edge clock.
Creating register for signal `\Data_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Data_Memory.v:26$29_DATA' using process `\Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:23$31'.
  created $dff cell `$procdff$260' with positive edge clock.
Creating register for signal `\Data_Memory.$memwr$\mem$/openlane/designs/Pipeline_top/src/Data_Memory.v:26$29_EN' using process `\Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:23$31'.
  created $dff cell `$procdff$261' with positive edge clock.

32. Executing PROC_MEMWR pass (convert process memory writes to cells).

33. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `fetch_cycle.$proc$/openlane/designs/Pipeline_top/src/Fetch_Cycle.v:64$196'.
Removing empty process `decode_cycle.$proc$/openlane/designs/Pipeline_top/src/Decode_Cyle.v:80$194'.
Removing empty process `execute_cycle.$proc$/openlane/designs/Pipeline_top/src/Execute_Cycle.v:88$191'.
Removing empty process `memory_cycle.$proc$/openlane/designs/Pipeline_top/src/Memory_Cycle.v:46$189'.
Found and cleaned up 1 empty switch in `\PC_Module.$proc$/openlane/designs/Pipeline_top/src/PC.v:21$187'.
Removing empty process `PC_Module.$proc$/openlane/designs/Pipeline_top/src/PC.v:21$187'.
Removing empty process `Instruction_Memory.$proc$/openlane/designs/Pipeline_top/src/Instruction_Memory.v:0$170'.
Removing empty process `Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:0$97'.
Found and cleaned up 1 empty switch in `\Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:24$81'.
Removing empty process `Register_File.$proc$/openlane/designs/Pipeline_top/src/Register_File.v:24$81'.
Removing empty process `Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:0$42'.
Found and cleaned up 1 empty switch in `\Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:23$31'.
Removing empty process `Data_Memory.$proc$/openlane/designs/Pipeline_top/src/Data_Memory.v:23$31'.
Cleaned up 3 empty switches.

34. Executing CHECK pass (checking for obvious problems).
Checking module Pipeline_top...
Checking module fetch_cycle...
Checking module decode_cycle...
Checking module execute_cycle...
Checking module memory_cycle...
Checking module writeback_cycle...
Checking module PC_Module...
Checking module PC_Adder...
Checking module Mux_3_by_1...
Checking module Mux...
Checking module Instruction_Memory...
Checking module Control_Unit_Top...
Checking module Main_Decoder...
Checking module ALU_Decoder...
Checking module Register_File...
Checking module Sign_Extend...
Checking module ALU...
Checking module Data_Memory...
Checking module hazard_unit...
Found and reported 0 problems.

35. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.
Optimizing module fetch_cycle.
<suppressed ~7 debug messages>
Optimizing module decode_cycle.
<suppressed ~1 debug messages>
Optimizing module execute_cycle.
<suppressed ~1 debug messages>
Optimizing module memory_cycle.
<suppressed ~1 debug messages>
Optimizing module writeback_cycle.
Optimizing module PC_Module.
<suppressed ~2 debug messages>
Optimizing module PC_Adder.
Optimizing module Mux_3_by_1.
<suppressed ~1 debug messages>
Optimizing module Mux.
<suppressed ~1 debug messages>
Optimizing module Instruction_Memory.
<suppressed ~2 debug messages>
Optimizing module Control_Unit_Top.
Optimizing module Main_Decoder.
Optimizing module ALU_Decoder.
<suppressed ~3 debug messages>
Optimizing module Register_File.
<suppressed ~5 debug messages>
Optimizing module Sign_Extend.
<suppressed ~1 debug messages>
Optimizing module ALU.
<suppressed ~3 debug messages>
Optimizing module Data_Memory.
<suppressed ~1 debug messages>
Optimizing module hazard_unit.
<suppressed ~12 debug messages>

36. Executing FLATTEN pass (flatten design).
Deleting now unused module fetch_cycle.
Deleting now unused module decode_cycle.
Deleting now unused module execute_cycle.
Deleting now unused module memory_cycle.
Deleting now unused module writeback_cycle.
Deleting now unused module PC_Module.
Deleting now unused module PC_Adder.
Deleting now unused module Mux_3_by_1.
Deleting now unused module Mux.
Deleting now unused module Instruction_Memory.
Deleting now unused module Control_Unit_Top.
Deleting now unused module Main_Decoder.
Deleting now unused module ALU_Decoder.
Deleting now unused module Register_File.
Deleting now unused module Sign_Extend.
Deleting now unused module ALU.
Deleting now unused module Data_Memory.
Deleting now unused module hazard_unit.
<suppressed ~22 debug messages>

37. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

38. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..
Removed 212 unused cells and 483 unused wires.
<suppressed ~457 debug messages>

39. Executing OPT pass (performing simple optimizations).

39.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

39.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

39.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Pipeline_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

39.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \Pipeline_top.
Performed a total of 0 changes.

39.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

39.6. Executing OPT_DFF pass (perform DFF optimizations).

39.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

39.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

39.9. Finished OPT passes. (There is nothing left to do.)

40. Executing FSM pass (extract and optimize FSM).

40.1. Executing FSM_DETECT pass (finding FSMs in design).

40.2. Executing FSM_EXTRACT pass (extracting FSM from design).

40.3. Executing FSM_OPT pass (simple optimizations of FSMs).

40.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

40.5. Executing FSM_OPT pass (simple optimizations of FSMs).

40.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

40.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

40.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

41. Executing OPT pass (performing simple optimizations).

41.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

41.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

41.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Pipeline_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

41.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \Pipeline_top.
Performed a total of 0 changes.

41.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

41.6. Executing OPT_DFF pass (perform DFF optimizations).

41.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

41.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

41.9. Finished OPT passes. (There is nothing left to do.)

42. Executing WREDUCE pass (reducing word size of cells).

43. Executing PEEPOPT pass (run peephole optimizers).

44. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

45. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module Pipeline_top:
  created 0 $alu and 0 $macc cells.

46. Executing SHARE pass (SAT-based resource sharing).

47. Executing OPT pass (performing simple optimizations).

47.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

47.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

47.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Pipeline_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

47.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \Pipeline_top.
Performed a total of 0 changes.

47.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

47.6. Executing OPT_DFF pass (perform DFF optimizations).

47.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

47.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

47.9. Finished OPT passes. (There is nothing left to do.)

48. Executing MEMORY pass.

48.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

48.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

48.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

48.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

48.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

48.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

48.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

48.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

48.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

48.10. Executing MEMORY_COLLECT pass (generating $mem cells).

49. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

50. Executing OPT pass (performing simple optimizations).

50.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

50.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

50.3. Executing OPT_DFF pass (perform DFF optimizations).

50.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

50.5. Finished fast OPT passes.

51. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

52. Executing OPT pass (performing simple optimizations).

52.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

52.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

52.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Pipeline_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

52.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \Pipeline_top.
Performed a total of 0 changes.

52.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

52.6. Executing OPT_SHARE pass.

52.7. Executing OPT_DFF pass (perform DFF optimizations).

52.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

52.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

52.10. Finished OPT passes. (There is nothing left to do.)

53. Executing TECHMAP pass (map to technology primitives).

53.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

53.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~73 debug messages>

54. Executing OPT pass (performing simple optimizations).

54.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

54.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

54.3. Executing OPT_DFF pass (perform DFF optimizations).

54.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

54.5. Finished fast OPT passes.

55. Executing ABC pass (technology mapping using ABC).

55.1. Extracting gate netlist of module `\Pipeline_top' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

56. Executing OPT pass (performing simple optimizations).

56.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

56.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

56.3. Executing OPT_DFF pass (perform DFF optimizations).

56.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

56.5. Finished fast OPT passes.

57. Executing HIERARCHY pass (managing design hierarchy).

57.1. Analyzing design hierarchy..
Top module:  \Pipeline_top

57.2. Analyzing design hierarchy..
Top module:  \Pipeline_top
Removed 0 unused modules.

58. Printing statistics.

=== Pipeline_top ===

   Number of wires:                 21
   Number of wire bits:             52
   Number of public wires:          21
   Number of public wire bits:      52
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

59. Executing CHECK pass (checking for obvious problems).
Checking module Pipeline_top...
Found and reported 0 problems.

60. Generating Graphviz representation of design.
Writing dot description to `/openlane/designs/Pipeline_top/runs/run1/tmp/synthesis/post_techmap.dot'.
Dumping module Pipeline_top to page 1.

61. Executing SHARE pass (SAT-based resource sharing).

62. Executing OPT pass (performing simple optimizations).

62.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

62.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

62.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Pipeline_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

62.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \Pipeline_top.
Performed a total of 0 changes.

62.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Pipeline_top'.
Removed a total of 0 cells.

62.6. Executing OPT_DFF pass (perform DFF optimizations).

62.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

62.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Pipeline_top.

62.9. Finished OPT passes. (There is nothing left to do.)

63. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..
Removed 0 unused cells and 19 unused wires.
<suppressed ~19 debug messages>

64. Printing statistics.

=== Pipeline_top ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

mapping tbuf

65. Executing TECHMAP pass (map to technology primitives).

65.1. Executing Verilog-2005 frontend: /home/ashutosh_anand/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
Parsing Verilog input from `/home/ashutosh_anand/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.

65.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>

66. Executing SIMPLEMAP pass (map simple cells to gate primitives).

67. Executing TECHMAP pass (map to technology primitives).

67.1. Executing Verilog-2005 frontend: /home/ashutosh_anand/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v
Parsing Verilog input from `/home/ashutosh_anand/.volare/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Successfully finished Verilog frontend.

67.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

68. Executing SIMPLEMAP pass (map simple cells to gate primitives).

69. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

69.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\Pipeline_top':

70. Printing statistics.

=== Pipeline_top ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

[INFO]: USING STRATEGY AREA 0

71. Executing ABC pass (technology mapping using ABC).

71.1. Extracting gate netlist of module `\Pipeline_top' to `/tmp/yosys-abc-c0ulH0/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

72. Executing SETUNDEF pass (replace undef values with defined constants).

73. Executing HILOMAP pass (mapping to constant drivers).

74. Executing SPLITNETS pass (splitting up multi-bit signals).

75. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Pipeline_top..

76. Executing INSBUF pass (insert buffer cells for connected wires).

77. Executing CHECK pass (checking for obvious problems).
Checking module Pipeline_top...
Found and reported 0 problems.

78. Printing statistics.

=== Pipeline_top ===

   Number of wires:                  2
   Number of wire bits:              2
   Number of public wires:           2
   Number of public wire bits:       2
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

79. Executing Verilog backend.
Dumping module `\Pipeline_top'.

80. Executing JSON backend.

End of script. Logfile hash: 1f6996f824, CPU: user 0.37s system 0.00s, MEM: 28.44 MB peak
Yosys 0.34 (git sha1 4a1b5599258, gcc 8.3.1 -fPIC -Os)
Time spent: 28% 4x stat (0 sec), 25% 1x dfflibmap (0 sec), ...
kareefardi commented 7 months ago

Can you post your configuration?

Ashutosh-3107 commented 7 months ago

Can you post your configuration?

set ::env(DESIGN_NAME) {Pipeline_top}
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/Hazard_unit.v $::env(DESIGN_DIR)/src/Data_Memory.v $::env(DESIGN_DIR)/src/ALU.v $::env(DESIGN_DIR)/src/Sign_Extend.v $::env(DESIGN_DIR)/src/Register_File.v $::env(DESIGN_DIR)/src/ALU_Decoder.v $::env(DESIGN_DIR)/src/Main_Decoder.v $::env(DESIGN_DIR)/src/Control_Unit_Top.v $::env(DESIGN_DIR)/src/Instruction_Memory.v $::env(DESIGN_DIR)/src/Mux.v $::env(DESIGN_DIR)/src/PC_Adder.v $::env(DESIGN_DIR)/src/PC.v $::env(DESIGN_DIR)/src/Writeback_Cycle.v $::env(DESIGN_DIR)/src/Memory_Cycle.v $::env(DESIGN_DIR)/src/Execute_Cycle.v $::env(DESIGN_DIR)/src/Decode_Cyle.v $::env(DESIGN_DIR)/src/Fetch_Cycle.v $::env(DESIGN_DIR)/src/Pipeline_top.v]
#set   ::env(SYNTH_HIERARCHICAL) 1
#set  ::env(SYNTH_FLAT_TOP) 0
#set ::env(SYNTH_STRATEGY) {DELAY 1}
#set ::env(SYNTH_NO_FLAT) 1
set ::env(SYNTH_EXPLORE) 0
set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_PERIOD) "80.0"

#set ::env(FP_PDN_MULTILAYER) {1}

set tech_specific_config "$::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl"
if { [file exists $tech_specific_config] == 1 } {
    source $tech_specific_config
}
kareefardi commented 7 months ago

@Ashutosh-3107 The design has no output ports. There is nothing to drive by the top level module making everything unused and Yosys removes unused wires and cells.